source: trunk/MultiChannelUSB

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Diff Rev Age Author Log Message
(edit) @174   13 years demin replace HOMEPATH with HOME
(edit) @173   13 years demin remove overflow bins
(edit) @172   13 years demin remove overflow bins
(edit) @171   13 years demin add initialization for after variable
(edit) @170   13 years demin add information header to histogram file
(edit) @169   13 years demin add region of interest to histogram view
(edit) @168   13 years demin add "Read file" button to histogram and counter views
(edit) @167   14 years demin multiple GUI fixes
(edit) @166   14 years demin fix histogram connections
(edit) @165   14 years demin switch to 10000 bins for the rate histogram
(edit) @164   14 years demin switch to 10000 bins
(edit) @163   14 years demin switch from 16384 to 4096 bins
(edit) @162   14 years demin add spectrum histogram 2
(edit) @161   14 years demin add multiplexers for spectrum and rate histograms
(edit) @160   14 years demin seems like Paella.dpf is not needed
(edit) @159   14 years demin adapt to paella v2
(edit) @104   16 years demin rename clk to clock
(edit) @103   16 years demin add fourth oscilloscope channel
(edit) @101   16 years demin add exposure counter
(edit) @100   16 years demin multiple fixes
(edit) @99   16 years demin double the number of configuration registers
(edit) @98   16 years demin replace fixed value with parameter in the int_data_next assignment
(edit) @97   16 years demin rename several interface wires
(edit) @96   16 years demin multiple fixes
(edit) @95   16 years demin remove idle state
(edit) @94   16 years demin add exposure counter
(edit) @93   16 years demin add a few more samples
(edit) @92   16 years demin delay result by one more clock
(edit) @91   16 years demin fix communication with external SRAM
(edit) @90   16 years demin full rewrite
(edit) @89   16 years demin remove debug output
(edit) @88   16 years demin fix memory read timing
(edit) @87   16 years demin fix writing of the last EPT sample to SRAM
(edit) @86   16 years demin replace 3 ADC FIFO with one large FIFO
(edit) @85   16 years demin add possibility to record full EPT information
(edit) @84   16 years demin improve timings in all components
(edit) @83   16 years demin first working version
(edit) @82   16 years demin several minor fixes
(edit) @81   16 years demin activate all 3 ADC channels
(edit) @80   16 years demin simplify analyser interface
(edit) @79   16 years demin switch from 8 to 4 byte command
(edit) @78   16 years demin make configuration frame always visible
(edit) @77   16 years demin add configuration form and activate all channels
(edit) @76   16 years demin add counter between peaks
(edit) @75   16 years demin fix osc_mux and trg_mux
(edit) @74   16 years demin fix signal shape display configuration
(edit) @73   16 years demin first working version
(edit) @72   16 years demin testing all components together
(edit) @71   16 years demin move to central clock domain
(edit) @70   16 years demin intermediate working version with 32 bit histograms, test block and …
(edit) @69   16 years demin add I2C master
(edit) @68   16 years demin add I2C master and switch from 24 to 32 bit histogram
(edit) @67   16 years demin switch from 24 to 32 bit histogram
(edit) @66   16 years demin first working version
(edit) @65   16 years demin start testing SRAM
(edit) @64   16 years demin switch eab on
(edit) @63   16 years demin add parameters for number of channels and channel resolution
(edit) @62   16 years demin add polarity flag
(edit) @61   16 years demin add interface for parallel ADC with unreliable clock
(edit) @60   16 years demin interface for parallel ADC with unreliable clock
(edit) @59   16 years demin move control and test code to separate modules
(edit) @58   16 years demin code cleanup
(edit) @57   16 years demin switch to direct instantiation of altsyncram and dcfifo
(edit) @56   16 years demin switch to direct instantiation of altsyncram
(edit) @55   16 years demin add pll for lvds interface
(edit) @54   16 years demin adapat memory access to normal memory clock
(edit) @53   16 years demin add signal invertor
(edit) @52   16 years demin switch to normal memory clock
(edit) @51   16 years demin first attempt to use normal memory clock
(edit) @50   16 years demin fix peak detection logic and add peak threshold
(edit) @49   16 years demin add registers for output data
(edit) @48   16 years demin cleanup test circuit
(edit) @47   16 years demin switch to direct instantiation of altsyncram
(edit) @46   16 years demin use loop for addr and reset initialisation
(edit) @45   16 years demin add fourth channel and switch from 32 to 24 bit histogram
(edit) @44   16 years demin add baseline subtraction
(edit) @43   16 years demin put back lost PIN_98 and PIN_99
(edit) @42   16 years demin code cleanup
(edit) @41   16 years demin add one real ADC channel
(edit) @39   16 years demin add configuration for EPCS16
(edit) @38   16 years demin add serial flash loader
(edit) @37   16 years demin fix communication with fifo_rx_unit
(edit) @36   16 years demin several minor fixes
(edit) @35   16 years demin first working version
(edit) @34   16 years demin working test version
(edit) @33   16 years demin return to simple USB interface with some adjustments
(edit) @31   16 years demin attemp to improve USB interface
(edit) @30   16 years demin put all components in place
(edit) @29   16 years demin split USB_PA into separate wires
(add) @27   16 years demin initial commit
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