Changeset 34 for trunk/MultiChannelUSB

Timestamp:

Sep 7, 2009, 12:04:30 AM (15 years ago)

Author:

demin

Message:

working test version

File:

• trunk/MultiChannelUSB/Paella.v (modified) (5 diffs)

trunk/MultiChannelUSB/Paella.v

@@ -99 +99 @@
                 .usb_pktend(usb_pktend),
                 .usb_addr(usb_addr),
+
                 .clk(CLK_50MHz),
                 .aclr(usb_fifo_aclr),
-                .tx_wrreq(usb_fifo_tx_wrreq),
+
+                .tx_full(usb_fifo_tx_full),
+//              .tx_wrreq(usb_fifo_tx_wrreq),
+//              .tx_wrreq((~usb_fifo_tx_full) & (state1 == 3'd5)),
+                .tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
+                .tx_data(usb_fifo_tx_data),
+//              .tx_data(osc_counter),
+
+                .rx_empty(usb_fifo_rx_empty),
                 .rx_rdreq(usb_fifo_rx_rdreq),
-                .tx_data(usb_fifo_tx_data),
-                .tx_full(usb_fifo_tx_full),
-                .rx_empty(usb_fifo_rx_empty),
-                .rx_data(usb_fifo_rx_data),
+                .rx_q(usb_fifo_rx_data),
+                
                 .led(usb_fifo_led)
         );
         
-        reg             [9:0]   osc_counter;    
+        reg             [10:0]  osc_counter;    
         reg                     osc_reset;
         reg                     osc_byte_num;
@@ -204 +211 @@
                 endcase
         end
-
+/*
         always @(posedge CLK_50MHz)
         begin
@@ -267 +274 @@
                                         endcase
                                         
-                                        if (&hst_byte_num)
-                                        begin
-                                                if (&hst_addr)
-                                                begin
-                                                        state1 <= 3'd1;
-                                                end
-                                                else
-                                                begin
-                                                        hst_addr <= hst_addr + 12'd1;
-                                                end
+                                        if ((&hst_byte_num) & (&hst_addr))
+                                        begin
+                                                state1 <= 3'd1;
+                                        end
+                                        else if (&hst_byte_num)
+                                        begin
+                                                hst_addr <= hst_addr + 12'd1;
                                         end
 
                                         hst_byte_num <= hst_byte_num + 2'd1;                            
+                                end
+                        end
+
+                        4:
+                        begin
+                                usb_fifo_rx_rdreq <= 1'b0;
+                                usb_fifo_tx_wrreq <= 1'b0;
+                                usb_fifo_tx_data <= osc_counter;
+                            state1 <= 3'd5;
+                        end
+
+                        5:
+                        begin
+                                if (~usb_fifo_tx_full)
+                                begin
+                                        usb_fifo_tx_wrreq <= 1'b1;
+                                        state1 <= 3'd6;
+                                end
+                        end
+
+                        6:
+                        begin
+                                usb_fifo_tx_wrreq <= 1'b0;
+                                if (&osc_counter)
+                                begin
+                                        state1 <= 3'd1;
+                                end
+                                else
+                                begin
+                                        osc_counter <= osc_counter + 11'd1;
+                                        state1 <= 3'd4;
                                 end
                         end
@@ -290 +325 @@
                                 if(~usb_fifo_tx_full)
                                 begin
+                                        usb_fifo_tx_data <= osc_counter;
+                                        osc_counter <= osc_counter + 11'd1;
+                                        if (&osc_counter) state1 <= 3'd1;
+
                                         case (osc_byte_num)
                                                 1'd0: usb_fifo_tx_data <= osc_q[7:0];
                                                 1'd1: usb_fifo_tx_data <= osc_q[15:8];
                                         endcase
-        
-                                        if (osc_byte_num)
-                                        begin
-                                                if (&osc_counter)
-                                                begin
-                                                        state1 <= 3'd1;
-                                                end
-                                                else
-                                                begin
-                                                        osc_addr <= osc_addr + 10'd1;
-                                                        osc_counter <= osc_counter + 10'd1;
-                                                end
+
+                                        if ((osc_byte_num) & (&osc_counter))
+                                        begin
+                                                state1 <= 3'd1;
+                                        end
+                                        else if (osc_byte_num)
+                                        begin
+                                                osc_addr <= osc_addr + 10'd1;
+                                                osc_counter <= osc_counter + 10'd1;
                                         end
 
                                         osc_byte_num <= ~osc_byte_num;                          
+
                                 end
                         end
@@ -320 +357 @@
         end
 
-/*
+*/
         always @(posedge CLK_50MHz)
         begin
                 case(state1)
-                        0:
-                        begin
+                        1:
+                        begin
+                                usb_fifo_rx_rdreq <= 1'b0;
                                 usb_fifo_tx_wrreq <= 1'b0;
-                                counter <= 32'd0;
-                                state1 <= 3'd1;
-                        end
-                        1:
-                        begin
-                                if((~usb_fifo_tx_full) & (counter < 32'd512))
-                                begin
-                                        counter <= counter + 32'd1;
-                                        state1 <= 3'd2;
-                                        usb_fifo_tx_data <= 1;
-                                        usb_fifo_tx_wrreq <= 1'b1;
-                                end
-                                else
+                                hst_reset <= 1'b0;
+                                osc_reset <= 1'b0;
+                                state1 <= 3'd2;
+                        end
+
+                        2: 
+                        begin
+                                usb_fifo_rx_rdreq <= ~usb_fifo_rx_empty;
+                                if (~usb_fifo_rx_empty)
+                                begin
+                                        case (usb_fifo_rx_data)
+                                                8'h30:
+                                                begin
+                                                        hst_reset <= 1'b1;
+                                                        state1 <= 3'd1;
+                                                end
+                                                8'h31:
+                                                begin
+                                                        hst_addr <= 12'd0;
+                                                        hst_byte_num <= 2'd0;   
+                                                        state1 <= 3'd3;
+                                                end
+                                                8'h32:
+                                                begin
+                                                        led_reg <= 1'b1;
+                                                        osc_reset <= 1'b1;
+                                                        state1 <= 3'd1;
+                                                end
+                                                8'h33:
+                                                begin
+                                                        led_reg <= 1'b0;
+                                                        osc_addr <= osc_start_addr;
+                                                        osc_counter <= 11'd0;
+                                                        osc_byte_num <= 1'd0;   
+                                                        state1 <= 3'd4;
+                                                end
+
+                                        endcase
+                                end
+                        end
+                        4:
+                        begin
+                                usb_fifo_tx_data <= osc_counter;
+                                usb_fifo_tx_wrreq <= 1'b1;
+                                osc_counter <= osc_counter + 11'd1;
+                                state1 <= 3'd5;
+                        end
+                        5:
+                        begin
+                                if (~usb_fifo_tx_full)
+                                begin
+                                        usb_fifo_tx_data <= osc_counter;
+                                        if (osc_counter == 11'd0) //(&osc_counter)
+                                        begin
+                                                state1 <= 3'd6;
+                                        end
+                                        else
+                                        begin
+                                                osc_counter <= osc_counter + 11'd1;
+                                        end
+                                end
+                        end
+                        6:
+                        begin
+                                if (~usb_fifo_tx_full)
                                 begin
                                         usb_fifo_tx_wrreq <= 1'b0;
-                                end
-                        end
-                                
-                        2:
-                        begin
-                                if((~usb_fifo_tx_full) & (counter < 32'd512))
-                                begin
-                                        counter <= counter + 32'd1;
                                         state1 <= 3'd1;
-                                        usb_fifo_tx_data <= 0;
-                                        usb_fifo_tx_wrreq <= 1'b1;
-                                end
-                                else
-                                begin
-                                        usb_fifo_tx_wrreq <= 1'b0;
-                                end
-                        end
-                                                
-                        default: state1 <= 3'd0;
+                                end
+                        end
+
+                                                                                
+                        default: state1 <= 3'd1;
                 endcase
         end
-*/
+
         always @ (posedge adc_clk)
         begin