source: trunk/MultiChannelUSB/Paella.v@ 34

Last change on this file since 34 was 34, checked in by demin, 15 years ago

working test version
File size: 9.2 KB
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1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
15 input wire ADC_DB,
16 input wire ADC_DC,
17 input wire ADC_DD,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 // Turn output ports off
46 assign RAM_CLK = 1'b0;
47 assign RAM_CE1 = 1'b0;
48 assign RAM_WE = 1'b0;
49 assign RAM_ADDR = 20'h00000;
50
51 // Turn inout ports to tri-state
52 assign TRG = 4'bz;
53 assign CON_A = 7'bz;
54 assign CON_B = 16'bz;
55 assign CON_C = 13'bz;
56 assign USB_PA0 = 1'bz;
57 assign USB_PA1 = 1'bz;
58 assign USB_PA3 = 1'bz;
59 assign USB_PA7 = 1'bz;
60 assign RAM_DQAP = 1'bz;
61 assign RAM_DQA = 8'bz;
62 assign RAM_DQBP = 1'bz;
63 assign RAM_DQB = 8'bz;
64
65
66 assign USB_PA2 = ~usb_rden;
67 assign USB_PA4 = usb_addr[0];
68 assign USB_PA5 = usb_addr[1];
69 assign USB_PA6 = ~usb_pktend;
70
71 reg [31:0] counter;
72 reg led_reg;
73// assign LED = counter[24];
74// assign LED = ~usb_fifo_rx_empty;
75 assign LED = led_reg;
76// assign LED = usb_fifo_led;
77
78 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
79 wire usb_fifo_aclr, usb_fifo_led;
80 reg usb_fifo_tx_wrreq;
81 reg usb_fifo_rx_rdreq;
82 wire usb_fifo_tx_full, usb_fifo_rx_empty;
83 reg [7:0] usb_fifo_tx_data;
84 wire [7:0] usb_fifo_rx_data;
85 wire [1:0] usb_addr;
86
87 assign USB_SLRD = ~usb_rdreq;
88 assign USB_SLWR = ~usb_wrreq;
89
90 usb_fifo usb_fifo_unit
91 (
92 .usb_clk(USB_IFCLK),
93 .usb_data(USB_PB),
94 .usb_full(~USB_FLAGB),
95 .usb_empty(~USB_FLAGA),
96 .usb_wrreq(usb_wrreq),
97 .usb_rdreq(usb_rdreq),
98 .usb_rden(usb_rden),
99 .usb_pktend(usb_pktend),
100 .usb_addr(usb_addr),
101
102 .clk(CLK_50MHz),
103 .aclr(usb_fifo_aclr),
104
105 .tx_full(usb_fifo_tx_full),
106// .tx_wrreq(usb_fifo_tx_wrreq),
107// .tx_wrreq((~usb_fifo_tx_full) & (state1 == 3'd5)),
108 .tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
109 .tx_data(usb_fifo_tx_data),
110// .tx_data(osc_counter),
111
112 .rx_empty(usb_fifo_rx_empty),
113 .rx_rdreq(usb_fifo_rx_rdreq),
114 .rx_q(usb_fifo_rx_data),
115
116 .led(usb_fifo_led)
117 );
118
119 reg [10:0] osc_counter;
120 reg osc_reset;
121 reg osc_byte_num;
122 wire [9:0] osc_start_addr;
123 reg [9:0] osc_addr;
124 wire [15:0] osc_q;
125
126 reg hst_reset;
127 reg [1:0] hst_byte_num;
128 reg [11:0] hst_addr;
129 wire [31:0] hst_q;
130
131 reg [2:0] state0, state1, state2;
132 reg adc_fifo_rdreq;
133 wire adc_fifo_rdempty;
134 reg adc_fifo_aclr;
135
136 reg [31:0] adc_counter;
137 reg adc_data_ready;
138 wire adc_clk;
139 reg [11:0] adc_data;
140 wire [11:0] raw_data;
141 wire [11:0] uwt_data;
142 wire [1:0] uwt_flag;
143
144 pll pll_unit(
145 .inclk0(CLK_50MHz),
146 .c0(adc_clk));
147
148 adc_fifo adc_fifo_unit (
149 .adc_clk(adc_clk),
150 .adc_data(adc_data),
151 .aclr(adc_fifo_aclr),
152 .rdclk(CLK_50MHz),
153 .rdreq(adc_fifo_rdreq),
154 .rdempty(adc_fifo_rdempty),
155 .raw_data(raw_data),
156 .uwt_data({uwt_flag, uwt_data}));
157
158 histogram histogram_unit (
159 .clk(CLK_50MHz),
160 .reset(hst_reset),
161 .data_ready(adc_data_ready),
162 .data(raw_data),
163 .address(hst_addr),
164 .q(hst_q)
165 );
166
167 oscilloscope oscilloscope_unit (
168 .clk(CLK_50MHz),
169 .reset(osc_reset),
170 .data_ready(adc_data_ready),
171 .raw_data(raw_data),
172 .uwt_data(uwt_data),
173 .threshold(16'd100),
174 .address(osc_addr),
175 .start_address(osc_start_addr),
176 .q(osc_q)
177 );
178
179/*
180 always @ (posedge adc_clk)
181 begin
182 counter <= counter + 32'd1;
183 end
184*/
185
186 always @ (posedge CLK_50MHz)
187 begin
188 case (state0)
189 1:
190 begin
191 if (~adc_fifo_rdempty)
192 begin
193// adc_counter <= adc_counter + 32'd1;
194 adc_fifo_rdreq <= 1'b1;
195 adc_data_ready <= 1'b1;
196 state0 <= 3'd2;
197 end
198 end
199
200 2:
201 begin
202 adc_fifo_rdreq <= 1'b0;
203 adc_data_ready <= 1'b0;
204 state0 <= 3'd1;
205 end
206
207 default:
208 begin
209 state0 <= 3'd1;
210 end
211 endcase
212 end
213/*
214 always @(posedge CLK_50MHz)
215 begin
216 case (state1)
217 1:
218 begin
219 usb_fifo_rx_rdreq <= 1'b0;
220 usb_fifo_tx_wrreq <= 1'b0;
221 hst_reset <= 1'b0;
222 osc_reset <= 1'b0;
223 state1 <= 3'd2;
224 end
225
226 2:
227 begin
228 usb_fifo_rx_rdreq <= ~usb_fifo_rx_empty;
229 if (~usb_fifo_rx_empty)
230 begin
231 case (usb_fifo_rx_data)
232 8'h30:
233 begin
234 hst_reset <= 1'b1;
235 state1 <= 3'd1;
236 end
237 8'h31:
238 begin
239 led_reg <= 1'b1;
240 hst_addr <= 12'd0;
241 hst_byte_num <= 2'd0;
242 state1 <= 3'd3;
243 end
244 8'h32:
245 begin
246 osc_reset <= 1'b1;
247 state1 <= 3'd1;
248 end
249 8'h33:
250 begin
251 led_reg <= 1'b0;
252 osc_addr <= osc_start_addr;
253 osc_counter <= 10'd0;
254 osc_byte_num <= 1'd0;
255 state1 <= 3'd4;
256 end
257
258 endcase
259 end
260 end
261
262 3:
263 begin
264 // hst transfer
265 usb_fifo_rx_rdreq <= 1'b0;
266 usb_fifo_tx_wrreq <= ~usb_fifo_tx_full;
267 if (~usb_fifo_tx_full)
268 begin
269 case (hst_byte_num)
270 2'd0: usb_fifo_tx_data <= hst_q[7:0];
271 2'd1: usb_fifo_tx_data <= hst_q[15:8];
272 2'd2: usb_fifo_tx_data <= hst_q[23:16];
273 2'd3: usb_fifo_tx_data <= hst_q[31:24];
274 endcase
275
276 if ((&hst_byte_num) & (&hst_addr))
277 begin
278 state1 <= 3'd1;
279 end
280 else if (&hst_byte_num)
281 begin
282 hst_addr <= hst_addr + 12'd1;
283 end
284
285 hst_byte_num <= hst_byte_num + 2'd1;
286 end
287 end
288
289 4:
290 begin
291 usb_fifo_rx_rdreq <= 1'b0;
292 usb_fifo_tx_wrreq <= 1'b0;
293 usb_fifo_tx_data <= osc_counter;
294 state1 <= 3'd5;
295 end
296
297 5:
298 begin
299 if (~usb_fifo_tx_full)
300 begin
301 usb_fifo_tx_wrreq <= 1'b1;
302 state1 <= 3'd6;
303 end
304 end
305
306 6:
307 begin
308 usb_fifo_tx_wrreq <= 1'b0;
309 if (&osc_counter)
310 begin
311 state1 <= 3'd1;
312 end
313 else
314 begin
315 osc_counter <= osc_counter + 11'd1;
316 state1 <= 3'd4;
317 end
318 end
319
320 4:
321 begin
322 // osc transfer
323 usb_fifo_rx_rdreq <= 1'b0;
324 usb_fifo_tx_wrreq <= ~usb_fifo_tx_full;
325 if(~usb_fifo_tx_full)
326 begin
327 usb_fifo_tx_data <= osc_counter;
328 osc_counter <= osc_counter + 11'd1;
329 if (&osc_counter) state1 <= 3'd1;
330
331 case (osc_byte_num)
332 1'd0: usb_fifo_tx_data <= osc_q[7:0];
333 1'd1: usb_fifo_tx_data <= osc_q[15:8];
334 endcase
335
336 if ((osc_byte_num) & (&osc_counter))
337 begin
338 state1 <= 3'd1;
339 end
340 else if (osc_byte_num)
341 begin
342 osc_addr <= osc_addr + 10'd1;
343 osc_counter <= osc_counter + 10'd1;
344 end
345
346 osc_byte_num <= ~osc_byte_num;
347
348 end
349 end
350
351 default:
352 begin
353 // default state is the first one
354 state1 <= 3'd1;
355 end
356 endcase
357 end
358
359*/
360 always @(posedge CLK_50MHz)
361 begin
362 case(state1)
363 1:
364 begin
365 usb_fifo_rx_rdreq <= 1'b0;
366 usb_fifo_tx_wrreq <= 1'b0;
367 hst_reset <= 1'b0;
368 osc_reset <= 1'b0;
369 state1 <= 3'd2;
370 end
371
372 2:
373 begin
374 usb_fifo_rx_rdreq <= ~usb_fifo_rx_empty;
375 if (~usb_fifo_rx_empty)
376 begin
377 case (usb_fifo_rx_data)
378 8'h30:
379 begin
380 hst_reset <= 1'b1;
381 state1 <= 3'd1;
382 end
383 8'h31:
384 begin
385 hst_addr <= 12'd0;
386 hst_byte_num <= 2'd0;
387 state1 <= 3'd3;
388 end
389 8'h32:
390 begin
391 led_reg <= 1'b1;
392 osc_reset <= 1'b1;
393 state1 <= 3'd1;
394 end
395 8'h33:
396 begin
397 led_reg <= 1'b0;
398 osc_addr <= osc_start_addr;
399 osc_counter <= 11'd0;
400 osc_byte_num <= 1'd0;
401 state1 <= 3'd4;
402 end
403
404 endcase
405 end
406 end
407 4:
408 begin
409 usb_fifo_tx_data <= osc_counter;
410 usb_fifo_tx_wrreq <= 1'b1;
411 osc_counter <= osc_counter + 11'd1;
412 state1 <= 3'd5;
413 end
414 5:
415 begin
416 if (~usb_fifo_tx_full)
417 begin
418 usb_fifo_tx_data <= osc_counter;
419 if (osc_counter == 11'd0) //(&osc_counter)
420 begin
421 state1 <= 3'd6;
422 end
423 else
424 begin
425 osc_counter <= osc_counter + 11'd1;
426 end
427 end
428 end
429 6:
430 begin
431 if (~usb_fifo_tx_full)
432 begin
433 usb_fifo_tx_wrreq <= 1'b0;
434 state1 <= 3'd1;
435 end
436 end
437
438
439 default: state1 <= 3'd1;
440 endcase
441 end
442
443 always @ (posedge adc_clk)
444 begin
445 case (state2)
446 1:
447 begin
448 adc_data <= 12'd0;
449 state2 <= 3'd2;
450 end
451
452 2:
453 begin
454 adc_data <= 12'd1024;
455 state2 <= 3'd3;
456 end
457
458 3:
459 begin
460 adc_data <= 12'd2048;
461 state2 <= 3'd4;
462 end
463
464 4:
465 begin
466 adc_data <= 12'd3072;
467 state2 <= 3'd5;
468 end
469
470 5:
471 begin
472 adc_data <= 12'd4095;
473 state2 <= 3'd1;
474 end
475
476 default:
477 begin
478 state2 <= 3'd1;
479 end
480 endcase
481 end
482
483endmodule
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