Changeset 51 for trunk/MultiChannelUSB
- Timestamp:
- Sep 16, 2009, 12:52:02 PM (15 years ago)
- Location:
- trunk/MultiChannelUSB
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/MultiChannelUSB/histogram.v
r47 r51 9 9 // signal declaration 10 10 reg [3:0] state_reg, state_next; 11 reg flag_reg, flag_next; 11 12 reg wren_reg, wren_next; 12 13 reg [11:0] addr_reg, addr_next; … … 14 15 15 16 wire [23:0] q_a_wire, q_b_wire; 17 18 wire [11:0] addr_wire; 19 wire [23:0] data_wire; 20 21 assign addr_wire = (flag_reg) ? data : addr_reg; 22 assign data_wire = (flag_reg) ? (q_a_wire + 24'd1) : data_reg; 16 23 17 24 altsyncram #( … … 39 46 .width_byteena_a(1), 40 47 .width_byteena_b(1), 41 .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit 42 .wren_a 43 .clock0 44 .wren_b 45 .address_a (addr_reg),46 .address_b 47 .data_a (data_reg),48 .data_b 49 .q_a 50 .q_b 51 .aclr0 52 .aclr1 53 .addressstall_a 54 .addressstall_b 55 .byteena_a 56 .byteena_b 57 .clock1 58 .clocken0 59 .clocken1 60 .clocken2 61 .clocken3 62 .eccstatus 63 .rden_a 64 .rden_b 48 .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit( 49 .wren_a(wren_reg), 50 .clock0(~clk), 51 .wren_b(1'b0), 52 .address_a(addr_wire), 53 .address_b(address), 54 .data_a(data_wire), 55 .data_b(), 56 .q_a(q_a_wire), 57 .q_b(q_b_wire), 58 .aclr0(1'b0), 59 .aclr1(1'b0), 60 .addressstall_a(1'b0), 61 .addressstall_b(1'b0), 62 .byteena_a(1'b1), 63 .byteena_b(1'b1), 64 .clock1(1'b1), 65 .clocken0(1'b1), 66 .clocken1(1'b1), 67 .clocken2(1'b1), 68 .clocken3(1'b1), 69 .eccstatus(), 70 .rden_a(1'b1), 71 .rden_b(1'b1)); 65 72 66 73 // body … … 69 76 if (reset) 70 77 begin 78 flag_reg <= 1'b0; 79 wren_reg <= 1'b1; 80 addr_reg <= 12'd0; 81 data_reg <= 24'd0; 71 82 state_reg <= 4'b1; 72 83 end 73 84 else 74 85 begin 75 state_reg <= state_next;86 flag_reg <= flag_next; 76 87 wren_reg <= wren_next; 77 88 addr_reg <= addr_next; 78 89 data_reg <= data_next; 90 state_reg <= state_next; 79 91 end 80 92 end … … 82 94 always @* 83 95 begin 84 state_next = state_reg;96 flag_next = flag_reg; 85 97 wren_next = wren_reg; 86 98 addr_next = addr_reg; 87 99 data_next = data_reg; 100 state_next = state_reg; 88 101 case (state_reg) 89 0: ; // nothing to do 90 1: 102 0: 91 103 begin 92 // start reset 93 wren_next = 1'b1; 94 addr_next = 0; 95 data_next = 0; 96 state_next = 4'd2; 104 // nothing to do 105 flag_next = 1'b0; 106 wren_next = 1'b0; 107 addr_next = 12'd0; 108 data_next = 24'd0; 109 state_next = 4'd0; 97 110 end 98 99 2:111 112 1: 100 113 begin 101 114 // write zeros 102 115 if (&addr_reg) 103 116 begin 104 state_next = 4'd3; 117 flag_next = 1'b1; 118 wren_next = 1'b0; 119 state_next = 4'd2; 105 120 end 106 121 else … … 108 123 addr_next = addr_reg + 12'd1; 109 124 end 110 end 111 112 3:125 end 126 127 2: 113 128 begin 114 // read 115 wren_next = 1'b0; 116 if (&data_reg) 129 if (data_ready) 117 130 begin 118 state_next = 4'd0; 119 end 120 else if (data_ready) 121 begin 122 // set addr 123 addr_next = data; 124 state_next = 4'd4; 131 if (&q_a_wire) 132 begin 133 flag_next = 1'b0; 134 state_next = 4'd0; 135 end 136 else 137 begin 138 wren_next = 1'b1; 139 state_next = 4'd3; 140 end 125 141 end 126 142 end 127 143 128 4:144 3: 129 145 begin 130 // increment and write 131 wren_next = 1'b1; 132 data_next = q_a_wire + 24'd1; 133 state_next = 4'd3; 146 wren_next = 1'b0; 147 state_next = 4'd2; 134 148 end 135 149 136 150 default: 137 151 begin 152 flag_next = 1'b0; 153 wren_next = 1'b0; 154 addr_next = 12'd0; 155 data_next = 24'd0; 138 156 state_next = 4'd0; 139 157 end -
trunk/MultiChannelUSB/oscilloscope.v
r45 r51 11 11 // signal declaration 12 12 reg [3:0] state_reg, state_next; 13 13 reg flag_reg, flag_next; 14 14 reg wren_reg, wren_next; 15 15 reg [9:0] addr_reg, addr_next; … … 22 22 wire [15:0] q_wire; 23 23 24 ram1024x16 ram1024x16_unit ( 25 .clock(~clk), 26 .data(data_reg), 27 .rdaddress(address), 28 .wraddress(addr_reg), 29 .wren(wren_reg), 30 .q(q_wire)); 24 wire [15:0] data_wire; 25 26 assign data_wire = (flag_reg) ? raw_data : data_reg; 27 28 altsyncram #( 29 .address_reg_b("CLOCK0"), 30 .clock_enable_input_a("BYPASS"), 31 .clock_enable_input_b("BYPASS"), 32 .clock_enable_output_a("BYPASS"), 33 .clock_enable_output_b("BYPASS"), 34 .intended_device_family("Cyclone III"), 35 .lpm_type("altsyncram"), 36 .numwords_a(1024), 37 .numwords_b(1024), 38 .operation_mode("DUAL_PORT"), 39 .outdata_aclr_b("NONE"), 40 .outdata_reg_b("UNREGISTERED"), 41 .power_up_uninitialized("FALSE"), 42 .read_during_write_mode_mixed_ports("OLD_DATA"), 43 .widthad_a(10), 44 .widthad_b(10), 45 .width_a(16), 46 .width_b(16), 47 .width_byteena_a(1)) osc_ram_unit( 48 .wren_a(wren_reg), 49 .clock0(~clk), 50 .address_a(addr_reg), 51 .address_b(address), 52 .data_a(data_wire), 53 .q_b(q_wire), 54 .aclr0(1'b0), 55 .aclr1(1'b0), 56 .addressstall_a(1'b0), 57 .addressstall_b(1'b0), 58 .byteena_a(1'b1), 59 .byteena_b(1'b1), 60 .clock1(1'b1), 61 .clocken0(1'b1), 62 .clocken1(1'b1), 63 .clocken2(1'b1), 64 .clocken3(1'b1), 65 .data_b({16{1'b1}}), 66 .eccstatus(), 67 .q_a(), 68 .rden_a(1'b1), 69 .rden_b(1'b1), 70 .wren_b(1'b0)); 31 71 32 72 // body … … 36 76 begin 37 77 state_reg <= 4'b1; 78 flag_reg <= 1'b0; 79 wren_reg <= 1'b1; 80 addr_reg <= 10'd0; 81 data_reg <= 16'd0; 82 trig_reg <= 1'b0; 83 trig_addr_reg <= 10'd0; 84 counter_reg <= 10'd0; 38 85 end 39 86 else 40 87 begin 41 88 state_reg <= state_next; 89 flag_reg <= flag_next; 42 90 wren_reg <= wren_next; 43 91 addr_reg <= addr_next; … … 52 100 begin 53 101 state_next = state_reg; 102 flag_next = flag_reg; 54 103 wren_next = wren_reg; 55 104 addr_next = addr_reg; … … 60 109 61 110 case (state_reg) 62 0: ; // nothing to do 63 1: 111 0: 64 112 begin 65 // start reset 66 wren_next = 1'b1; 67 addr_next = 0; 68 data_next = 0; 69 trig_next = 0; 70 trig_addr_next = 0; 71 counter_next = 0; 72 state_next = 4'd2; 113 // nothing to do 114 state_next = 4'b0; 115 flag_next = 1'b0; 116 wren_next = 1'b0; 117 addr_next = 10'd0; 118 data_next = 16'd0; 119 trig_next = 1'b0; 120 trig_addr_next = 10'd0; 121 counter_next = 10'd0; 73 122 end 74 123 75 2:124 1: 76 125 begin 77 126 // write zeros 78 127 if (&addr_reg) 79 128 begin 129 flag_next = 1'b1; 80 130 wren_next = 1'b0; 81 state_next = 4'd 3;131 state_next = 4'd2; 82 132 end 83 133 else … … 87 137 end 88 138 139 2: 140 begin 141 if (data_ready) 142 begin 143 wren_next = 1'b1; 144 state_next = 4'd3; 145 end 146 end 147 89 148 3: 90 149 begin 150 // stop write 151 wren_next = 1'b0; 152 addr_next = addr_reg + 10'd1; 153 91 154 if (&counter_reg) 92 155 begin 156 flag_next = 1'b0; 93 157 state_next = 4'd0; 94 158 end 95 else if (data_ready)159 else 96 160 begin 97 // start write 98 wren_next = 1'b1; 99 data_next = raw_data; 161 state_next = 4'd2; 162 100 163 if ((~trig_reg) 101 164 & (counter_reg == 10'd512) … … 106 169 trig_addr_next = addr_reg; 107 170 end 108 state_next = 4'd4; 171 172 if (trig_reg | (counter_reg < 10'd512)) 173 begin 174 counter_next = counter_reg + 10'd1; 175 end 109 176 end 110 end111 112 4:113 begin114 // stop write115 wren_next = 1'b0;116 addr_next = addr_reg + 10'd1;117 if (trig_reg | (counter_reg < 10'd512))118 begin119 counter_next = counter_reg + 10'd1;120 end121 state_next = 4'd3;122 177 end 123 178 124 179 default: 125 180 begin 126 state_next = 4'd0; 181 state_next = 4'b0; 182 flag_next = 1'b0; 183 wren_next = 1'b0; 184 addr_next = 10'd0; 185 data_next = 16'd0; 186 trig_next = 1'b0; 187 trig_addr_next = 10'd0; 188 counter_next = 10'd0; 127 189 end 128 190 endcase
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