Changeset 71 for trunk/MultiChannelUSB
- Timestamp:
- Nov 25, 2009, 11:01:34 PM (15 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/MultiChannelUSB/i2c_fifo.v
r70 r71 7 7 8 8 inout wire i2c_sda, 9 output wire i2c_scl9 inout wire i2c_scl 10 10 ); 11 11 … … 18 18 reg [4:0] state; 19 19 20 assign i2c_clk = counter[8];21 22 20 assign i2c_sda = int_sdo ? 1'bz : 1'b0; 23 assign i2c_scl = int_scl | (int_clken ? ~i2c_clk: 1'b0);21 assign i2c_scl = int_scl | (int_clken ? counter[8] : 1'b0); 24 22 25 23 assign start = int_data[8]; 26 24 assign stop = int_data[9]; 27 25 28 dcfifo #( 26 scfifo #( 27 .add_ram_output_register("OFF"), 29 28 .intended_device_family("Cyclone III"), 30 29 .lpm_numwords(16), 31 30 .lpm_showahead("ON"), 32 .lpm_type(" dcfifo"),31 .lpm_type("scfifo"), 33 32 .lpm_width(16), 34 33 .lpm_widthu(4), 35 .rdsync_delaypipe(4),36 .wrsync_delaypipe(4),37 34 .overflow_checking("ON"), 38 35 .underflow_checking("ON"), 39 .use_eab("OFF") ,40 . write_aclr_synch("OFF")) fifo_tx (36 .use_eab("OFF")) fifo_tx ( 37 .rdreq((~int_rdempty) & (int_rdreq) & (&counter)), 41 38 .aclr(aclr), 39 .clock(clk), 40 .wrreq(wrreq), 42 41 .data(data), 43 .rdclk(i2c_clk), 44 .rdreq((~int_rdempty) & int_rdreq), 45 .wrclk(clk), 46 .wrreq(wrreq), 42 .empty(int_rdempty), 47 43 .q(int_q), 48 .rdempty(int_rdempty), 49 .wrfull(full), 50 .rdfull(), 51 .rdusedw(), 52 .wrempty(), 53 .wrusedw()); 44 .full(full), 45 .almost_empty(), 46 .almost_full(), 47 .sclr(), 48 .usedw()); 54 49 55 50 always @ (posedge clk) 56 51 begin 57 52 counter <= counter + 9'd1; 58 end 59 60 always @ (posedge i2c_clk) 61 begin 62 case (state) 63 0: 64 begin 65 int_ack <= 1'b0; 66 int_sdo <= 1'b1; 67 int_scl <= 1'b1; 68 int_rdreq <= 1'b1; 69 state <= 5'd1; 70 end 71 72 1: 73 begin 74 if (~int_rdempty) 53 if (&counter) 54 begin 55 case (state) 56 0: 75 57 begin 76 int_data <= int_q; 58 int_ack <= 1'b0; 59 int_sdo <= 1'b1; 60 int_scl <= 1'b1; 61 int_rdreq <= 1'b1; 62 state <= 5'd1; 63 end 64 65 1: 66 begin 67 if (~int_rdempty) 68 begin 69 int_data <= int_q; 70 int_rdreq <= 1'b0; 71 state <= 5'd2; 72 end 73 end 74 75 2: 76 begin 77 if (start) 78 begin 79 int_sdo <= 1'b1; 80 int_scl <= 1'b1; 81 state <= 5'd3; 82 end 83 else 84 begin 85 state <= 5'd5; 86 end 87 end 88 89 3: 90 begin // start 91 int_sdo <= 1'b0; 92 state <= 5'd4; 93 end 94 95 4: 96 begin 97 int_scl <= 1'b0; 98 state <= 5'd5; 99 end 100 101 5: 102 begin // data 103 int_clken <= 1'b1; 104 int_sdo <= int_data[7]; 105 state <= 5'd6; 106 end 107 108 6: 109 begin 110 int_sdo <= int_data[6]; 111 state <= 5'd7; 112 end 113 114 7: 115 begin 116 int_sdo <= int_data[5]; 117 state <= 5'd8; 118 end 119 120 8: 121 begin 122 int_sdo <= int_data[4]; 123 state <= 5'd9; 124 end 125 126 9: 127 begin 128 int_sdo <= int_data[3]; 129 state <= 5'd10; 130 end 131 132 10: 133 begin 134 int_sdo <= int_data[2]; 135 state <= 5'd11; 136 end 137 138 11: 139 begin 140 int_sdo <= int_data[1]; 141 state <= 5'd12; 142 end 143 144 12: 145 begin 146 int_sdo <= int_data[0]; 147 state <= 5'd13; 148 end 149 150 13: 151 begin // ack 152 int_sdo <= 1'b1; 153 int_rdreq <= 1'b1; 154 state <= 5'd14; 155 end 156 157 14: 158 begin 159 int_ack <= i2c_sda; 77 160 int_rdreq <= 1'b0; 78 state <= 5'd2; 161 if (stop | int_rdempty) 162 begin 163 int_clken <= 1'b0; 164 int_sdo <= 1'b0; 165 int_scl <= 1'b0; 166 state <= 5'd15; 167 end 168 else if (~int_rdempty) 169 begin 170 int_data <= int_q; 171 int_sdo <= int_q[7]; 172 state <= 5'd6; 173 end 79 174 end 80 end 81 82 2: 83 begin 84 if (start) 175 176 15: 177 begin // stop 178 int_scl <= 1'b1; 179 state <= 5'd16; 180 end 181 182 16: 85 183 begin 86 184 int_sdo <= 1'b1; 87 int_scl <= 1'b1; 88 state <= 5'd3; 185 state <= 5'd0; 89 186 end 90 else 91 begin 92 state <= 5'd5; 93 end 94 end 95 96 3: 97 begin // start 98 int_sdo <= 1'b0; 99 state <= 5'd4; 100 end 101 102 4: 103 begin 104 int_scl <= 1'b0; 105 state <= 5'd5; 106 end 107 108 5: 109 begin // data 110 int_clken <= 1'b1; 111 int_sdo <= int_data[7]; 112 state <= 5'd6; 113 end 114 115 6: 116 begin 117 int_sdo <= int_data[6]; 118 state <= 5'd7; 119 end 120 121 7: 122 begin 123 int_sdo <= int_data[5]; 124 state <= 5'd8; 125 end 126 127 8: 128 begin 129 int_sdo <= int_data[4]; 130 state <= 5'd9; 131 end 132 133 9: 134 begin 135 int_sdo <= int_data[3]; 136 state <= 5'd10; 137 end 138 139 10: 140 begin 141 int_sdo <= int_data[2]; 142 state <= 5'd11; 143 end 144 145 11: 146 begin 147 int_sdo <= int_data[1]; 148 state <= 5'd12; 149 end 150 151 12: 152 begin 153 int_sdo <= int_data[0]; 154 state <= 5'd13; 155 end 156 157 13: 158 begin // ack 159 int_sdo <= 1'b1; 160 int_rdreq <= 1'b1; 161 state <= 5'd14; 162 end 163 164 14: 165 begin 166 int_ack <= i2c_sda; 167 int_rdreq <= 1'b0; 168 if (stop | int_rdempty) 169 begin 170 int_clken <= 1'b0; 171 int_sdo <= 1'b0; 172 int_scl <= 1'b0; 173 state <= 5'd15; 174 end 175 else if (~int_rdempty) 176 begin 177 int_data <= int_q; 178 int_sdo <= int_q[7]; 179 state <= 5'd6; 180 end 181 end 182 183 15: 184 begin // stop 185 int_scl <= 1'b1; 186 state <= 5'd16; 187 end 188 189 16: 190 begin 191 int_sdo <= 1'b1; 192 state <= 5'd0; 193 end 194 195 endcase 187 188 endcase 189 end 196 190 end 197 191
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