Changeset 72 for trunk/MultiChannelUSB
- Timestamp:
- Nov 25, 2009, 11:02:29 PM (15 years ago)
- Location:
- trunk/MultiChannelUSB
- Files:
-
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/MultiChannelUSB/Paella.qsf
r69 r72 56 56 set_global_assignment -name VERILOG_FILE control.v 57 57 set_global_assignment -name VERILOG_FILE analyser.v 58 set_global_assignment -name VERILOG_FILE baseline.v 58 59 set_global_assignment -name VERILOG_FILE histogram.v 60 set_global_assignment -name VERILOG_FILE trigger.v 59 61 set_global_assignment -name VERILOG_FILE oscilloscope.v 60 62 set_global_assignment -name VERILOG_FILE usb_fifo.v -
trunk/MultiChannelUSB/Paella.v
r70 r72 6 6 inout wire [3:0] TRG, 7 7 inout wire I2C_SDA, 8 output wire I2C_SCL,8 inout wire I2C_SCL, 9 9 inout wire [4:0] CON_A, 10 10 inout wire [15:0] CON_B, … … 43 43 ); 44 44 45 localparam N = 3; 46 45 47 // Turn output ports off 46 48 /* … … 105 107 ); 106 108 107 reg ana_reset [3:0]; 108 wire ana_peak_ready [3:0]; 109 wire [11:0] ana_peak [3:0]; 110 111 reg osc_reset [3:0]; 112 reg [9:0] osc_addr [3:0]; 113 wire [9:0] osc_start_addr [3:0]; 114 wire [15:0] osc_q [3:0]; 115 116 reg hst_reset [3:0]; 117 reg [11:0] hst_addr [3:0]; 118 wire [31:0] hst_q [3:0]; 109 reg bln_reset [N-1:0]; 110 wire [11:0] baseline [N-1:0]; 111 wire [11:0] bln_baseline [N-1:0]; 112 113 reg ana_reset [N-1:0]; 114 wire ana_peak_ready [N-1:0]; 115 wire [11:0] ana_peak [N-1:0]; 116 117 reg osc_reset [N-1:0]; 118 reg [9:0] osc_addr [N-1:0]; 119 wire [9:0] osc_start_addr [N-1:0]; 120 wire [15:0] osc_q [N-1:0]; 121 wire osc_trig [N-1:0]; 122 123 wire [3:0] osc_mux_sel [N-1:0]; 124 wire [11:0] osc_mux_data [N-1:0]; 125 126 wire trg_reset [N-1:0]; 127 wire [3:0] trg_mux_sel [N-1:0]; 128 wire [11:0] trg_mux_data [N-1:0]; 129 wire [11:0] trg_thrs [N-1:0]; 130 131 reg hst_reset [N-1:0]; 132 reg [11:0] hst_addr [N-1:0]; 133 wire hst_data_ready [N-1:0]; 134 wire [11:0] hst_data [N-1:0]; 135 wire [31:0] hst_q [N-1:0]; 136 137 138 wire [3:0] hst_mux_sel [N-1:0]; 139 wire [12:0] hst_mux_data [N-1:0]; 140 141 wire [3:0] bln_mux_sel [N-1:0]; 142 wire [11:0] bln_mux_data [N-1:0]; 119 143 120 144 wire mux_reset, mux_type; … … 126 150 reg [15:0] mux_min_addr, mux_max_addr; 127 151 128 wire adc_clk [3:0]; 129 wire adc_data_ready [3:0]; 130 wire [11:0] adc_data [3:0]; 131 132 wire [11:0] raw_data [3:0]; 133 wire [11:0] uwt_data [3:0]; 134 wire [1:0] uwt_flag [3:0]; 152 wire adc_clk [N-1:0]; 153 wire [11:0] adc_data [N-1:0]; 154 155 wire data_ready [N-1:0]; 156 wire [11:0] data [N-1:0]; 157 wire [11:0] int_data [N-1:0]; 135 158 136 wire [16:0] osc_thrs [3:0]; 137 wire adc_pola [3:0]; 138 159 /* 139 160 assign osc_thrs[0] = 16'd40; 140 161 assign osc_thrs[1] = 16'd60; 141 162 assign osc_thrs[2] = 16'd40; 142 163 assign osc_thrs[3] = 16'd1650; 143 144 assign adc_pola[0] = 1'b1; 145 assign adc_pola[1] = 1'b1; 146 assign adc_pola[2] = 1'b1; 147 assign adc_pola[3] = 1'b0; 164 */ 165 wire [31:0] uwt_d1 [N-1:0]; 166 wire [31:0] uwt_a1 [N-1:0]; 167 wire [31:0] uwt_peak1 [N-1:0]; 168 wire [31:0] uwt_d2 [N-1:0]; 169 wire [31:0] uwt_a2 [N-1:0]; 170 wire [31:0] uwt_peak2 [N-1:0]; 171 wire [31:0] uwt_d3 [N-1:0]; 172 wire [31:0] uwt_a3 [N-1:0]; 173 wire [31:0] uwt_peak3 [N-1:0]; 174 175 wire [1:0] uwt_flag1 [N-1:0]; 176 wire [1:0] uwt_flag2 [N-1:0]; 177 wire [1:0] uwt_flag3 [N-1:0]; 148 178 149 179 assign adc_clk[0] = ADC_FCO; 150 180 assign adc_clk[1] = ADC_FCO; 151 181 // assign adc_clk[2] = ADC_FCO; 152 182 /* 153 183 assign adc_clk[3] = ADC_FCO; 184 */ 154 185 /* 155 186 assign adc_clk[3] = CON_CCLK[0]; … … 196 227 .sdoin()); 197 228 */ 198 /* 229 199 230 adc_lvds #( 200 .size( 3),231 .size(2), 201 232 .width(12)) adc_lvds_unit ( 202 233 .lvds_dco(ADC_DCO), 203 234 // .lvds_dco(adc_pll_clk), 204 235 .lvds_fco(ADC_FCO), 205 .lvds_d(ADC_D), 206 .adc_data({ adc_data[0], 207 adc_data[1], 208 adc_data[2] })); 209 */ 236 .lvds_d(ADC_D[1:0]), 237 .adc_data({ adc_data[1], 238 adc_data[0] })); 239 240 241 reg [15:0] cfg_memory [31:0]; 242 wire [15:0] cfg_src_data; 243 wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr; 244 245 wire cfg_polarity [N-1:0]; 246 wire [11:0] cfg_baseline [N-1:0]; 247 wire [11:0] cfg_hst_threshold [N-1:0]; 248 wire [11:0] cfg_trg_threshold [N-1:0]; 249 250 wire cfg_reset; 251 252 integer j; 253 254 always @(posedge CLK_50MHz) 255 begin 256 if (cfg_reset) 257 begin 258 for(j = 0; j <= 31; j = j + 1) 259 begin 260 cfg_memory[j] <= 16'd0; 261 end 262 end 263 else 264 begin 265 cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data; 266 end 267 end 268 210 269 genvar i; 270 211 271 generate 212 for (i = 0; i < 3; i = i + 1)272 for (i = 0; i < N; i = i + 1) 213 273 begin : MCA_CHAIN 274 275 assign cfg_polarity[i] = cfg_memory[10][4*i]; 276 assign cfg_baseline[i] = cfg_memory[11+i][11:0]; 277 assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0]; 278 assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0]; 279 280 assign osc_mux_sel[i] = cfg_memory[20+i][3:0]; 281 assign trg_mux_sel[i] = cfg_memory[20+i][7:4]; 282 assign hst_mux_sel[i] = cfg_memory[20+i][11:8]; 283 assign bln_mux_sel[i] = cfg_memory[20+i][15:12]; 284 214 285 adc_fifo adc_fifo_unit ( 215 286 .adc_clk(adc_clk[i]), 216 287 .adc_data(adc_data[i]), 217 .polarity(adc_pola[i]), 218 .clk(CLK_50MHz), 219 .ready(adc_data_ready[i]), 220 .raw_data(raw_data[i]), 221 .uwt_data({uwt_flag[i], uwt_data[i]})); 288 .clk(CLK_50MHz), 289 .data_ready(data_ready[i]), 290 .data(int_data[i])); 291 292 assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]); 293 294 uwt_bior31 #(.L(1)) uwt_1_unit ( 295 .clk(CLK_50MHz), 296 .data_ready(data_ready[i]), 297 .x({20'h00000, data[i]}), 298 .d(uwt_d1[i]), 299 .a(uwt_a1[i]), 300 .peak(uwt_peak1[i]), 301 .flag(uwt_flag1[i])); 302 303 uwt_bior31 #(.L(2)) uwt_2_unit ( 304 .clk(CLK_50MHz), 305 .data_ready(data_ready[i]), 306 .x(uwt_a1[i]), 307 .d(uwt_d2[i]), 308 .a(uwt_a2[i]), 309 .peak(uwt_peak2[i]), 310 .flag(uwt_flag2[i])); 311 312 uwt_bior31 #(.L(3)) uwt_3_unit ( 313 .clk(CLK_50MHz), 314 .data_ready(data_ready[i]), 315 .x(uwt_a2[i]), 316 .d(uwt_d3[i]), 317 .a(uwt_a3[i]), 318 .peak(uwt_peak3[i]), 319 .flag(uwt_flag3[i])); 320 321 lpm_mux #( 322 .lpm_size(4), 323 .lpm_type("LPM_MUX"), 324 .lpm_width(12), 325 .lpm_widths(2)) osc_mux_unit ( 326 .sel(osc_mux_sel[i][1:0]), 327 .data({ uwt_a3[i][20:9], 328 uwt_a2[i][17:6], 329 uwt_a1[i][14:3], 330 data[i] }), 331 .result(osc_mux_data[i])); 332 333 lpm_mux #( 334 .lpm_size(4), 335 .lpm_type("LPM_MUX"), 336 .lpm_width(12), 337 .lpm_widths(2)) trg_mux_unit ( 338 .sel(trg_mux_sel[i][1:0]), 339 .data({ uwt_a3[i][20:9], 340 uwt_a2[i][17:6], 341 uwt_a1[i][14:3], 342 data[i] }), 343 .result(trg_mux_data[i])); 344 345 lpm_mux #( 346 .lpm_size(2), 347 .lpm_type("LPM_MUX"), 348 .lpm_width(13), 349 .lpm_widths(1)) hst_mux_unit ( 350 .sel(hst_mux_sel[i][0]), 351 .data({ {ana_peak[i], ana_peak_ready[i]}, 352 {data[i], data_ready[i]} }), 353 .result(hst_mux_data[i])); 222 354 355 lpm_mux #( 356 .lpm_size(2), 357 .lpm_type("LPM_MUX"), 358 .lpm_width(12), 359 .lpm_widths(1)) bln_mux_unit ( 360 .sel(bln_mux_sel[i][0]), 361 .data({bln_baseline[i], cfg_baseline[i]}), 362 .result(bln_mux_data[i])); 363 364 baseline baseline_unit ( 365 .clk(CLK_50MHz), 366 .reset(bln_reset[i]), 367 .data_ready(data_ready[i]), 368 .uwt_flag(uwt_flag3[i]), 369 .uwt_data(uwt_peak3[i]), 370 .baseline(bln_baseline[i])); 371 223 372 analyser analyser_unit ( 224 373 .clk(CLK_50MHz), 225 374 .reset(ana_reset[i]), 226 .data_ready(adc_data_ready[i]), 227 .uwt_flag(uwt_flag[i]), 228 .uwt_data(uwt_data[i]), 229 .threshold(12'd10), 375 .data_ready(data_ready[i]), 376 .uwt_flag(uwt_flag3[i]), 377 .uwt_data(uwt_peak3[i]), 230 378 .peak_ready(ana_peak_ready[i]), 231 379 .peak(ana_peak[i])); 232 380 233 histogram histogram_unit ( 381 assign hst_data[i] = (hst_mux_data[i][12:1] > bln_mux_data[i]) ? (hst_mux_data[i][12:1] - bln_mux_data[i]) : 12'd0; 382 assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]); 383 384 histogram #(.W(32)) histogram_unit ( 234 385 .clk(CLK_50MHz), 235 386 .reset(hst_reset[i]), 236 .data_ready(adc_data_ready[i]), 237 .data(raw_data[i]), 238 // .data(uwt_data[i]), 387 .data_ready(hst_data_ready[i]), 388 .data(hst_data[i]), 239 389 .address(hst_addr[i]), 240 390 .q(hst_q[i])); 241 /* 242 histogram histogram_unit ( 243 .clk(CLK_50MHz), 244 .reset(hst_reset[i]), 245 .data_ready(ana_peak_ready[i]), 246 .data(ana_peak[i]), 247 .address(hst_addr[i]), 248 .q(hst_q[i])); 249 */ 391 392 trigger trigger_unit ( 393 .clk(CLK_50MHz), 394 .reset(trg_reset[i]), 395 .data_ready(data_ready[i]), 396 .data(trg_mux_data[i]), 397 .threshold(cfg_trg_threshold[i]), 398 .trigger(osc_trig[i])); 399 400 250 401 oscilloscope oscilloscope_unit ( 251 402 .clk(CLK_50MHz), 252 403 .reset(osc_reset[i]), 253 .data_ready(adc_data_ready[i]), 254 .raw_data(raw_data[i]), 255 .uwt_data(uwt_data[i]), 256 .threshold(osc_thrs[i]), 404 .data_ready(data_ready[i]), 405 .data(osc_mux_data[i]), 406 .trigger(osc_trig[i]), 257 407 .address(osc_addr[i]), 258 408 .start_address(osc_start_addr[i]), … … 261 411 endgenerate 262 412 263 integer j;264 265 413 always @* 266 414 begin 267 for (j = 0; j < 4; j = j + 1)415 for (j = 0; j < N; j = j + 1) 268 416 begin 269 417 osc_reset[j] = 1'b0; … … 273 421 end 274 422 275 case({mux_type, mux_chan}) 276 3'b000, 3'b001, 3'b010, 3'b011: 423 case(mux_type) 424 // case({mux_type, mux_chan}) 425 1'b0: 426 // 3'b000, 3'b001, 3'b010, 3'b011: 277 427 begin 278 428 osc_reset[mux_chan] = mux_reset; … … 283 433 end 284 434 285 3'b100, 3'b101, 3'b110, 3'b111: 435 1'b1: 436 // 3'b100, 3'b101, 3'b110, 3'b011: 286 437 begin 287 438 hst_reset[mux_chan] = mux_reset; … … 332 483 control control_unit ( 333 484 .clk(CLK_50MHz), 485 .cfg_reset(cfg_reset), 486 .cfg_src_data(cfg_memory[cfg_src_addr[4:0]]), 487 .cfg_src_addr(cfg_src_addr), 488 .cfg_dst_data(cfg_dst_data), 489 .cfg_dst_addr(cfg_dst_addr), 334 490 .rx_empty(usb_rx_empty), 335 491 .tx_full(usb_tx_full), -
trunk/MultiChannelUSB/adc_fifo.v
r64 r72 3 3 input wire adc_clk, 4 4 input wire [11:0] adc_data, 5 input wire polarity,6 5 7 6 input wire clk, 8 9 output wire ready, 10 output wire [11:0] raw_data, 11 output wire [13:0] uwt_data 7 output wire data_ready, 8 output wire [11:0] data 12 9 ); 13 10 14 wire [31:0] uwt_d1, uwt_a1, uwt_peak1; 15 wire [31:0] uwt_d2, uwt_a2, uwt_peak2; 16 wire [31:0] uwt_d3, uwt_a3, uwt_peak3; 17 wire [1:0] uwt_flag1, uwt_flag2, uwt_flag3; 18 19 wire [11:0] int_raw_q; 20 wire [13:0] int_uwt_q; 21 22 reg [11:0] int_raw_data; 23 reg [13:0] int_uwt_data; 24 25 wire [1:0] wrfull; 11 wire [11:0] int_q; 12 reg [11:0] int_data; 26 13 27 reg state; 28 reg int_rdreq, int_ready; 29 wire int_rdempty; 30 31 wire [11:0] int_adc_data; 32 assign int_adc_data = (polarity) ? (12'hfff - adc_data) : (adc_data); 33 34 uwt_bior31 #(.L(1)) uwt_1_unit ( 35 .clk(adc_clk), 36 .x({20'h00000, int_adc_data}), 37 .d(uwt_d1), 38 .a(uwt_a1), 39 .peak(uwt_peak1), 40 .flag(uwt_flag1)); 41 42 uwt_bior31 #(.L(2)) uwt_2_unit ( 43 .clk(adc_clk), 44 .x(uwt_a1), 45 .d(uwt_d2), 46 .a(uwt_a2), 47 .peak(uwt_peak2), 48 .flag(uwt_flag2)); 49 50 uwt_bior31 #(.L(3)) uwt_3_unit ( 51 .clk(adc_clk), 52 .x(uwt_a2), 53 .d(uwt_d3), 54 .a(uwt_a3), 55 .peak(uwt_peak3), 56 .flag(uwt_flag3)); 14 reg state, int_rdreq, int_data_ready; 15 wire int_wrfull, int_rdempty; 57 16 58 17 dcfifo #( … … 67 26 .overflow_checking("ON"), 68 27 .underflow_checking("ON"), 69 .use_eab("O N"),70 .write_aclr_synch("OFF")) fifo_ raw(28 .use_eab("OFF"), 29 .write_aclr_synch("OFF")) fifo_unit ( 71 30 .aclr(1'b0), 72 .data( int_adc_data),31 .data(adc_data), 73 32 .rdclk(clk), 74 33 .rdreq((~int_rdempty) & int_rdreq), 75 34 .wrclk(adc_clk), 76 .wrreq(~ wrfull[0]),77 .q(int_ raw_q),35 .wrreq(~int_wrfull), 36 .q(int_q), 78 37 .rdempty(int_rdempty), 79 .wrfull(wrfull[0]), 80 .rdfull(), 81 .rdusedw(), 82 .wrempty(), 83 .wrusedw()); 84 85 dcfifo #( 86 .intended_device_family("Cyclone III"), 87 .lpm_numwords(16), 88 .lpm_showahead("ON"), 89 .lpm_type("dcfifo"), 90 .lpm_width(14), 91 .lpm_widthu(4), 92 .rdsync_delaypipe(4), 93 .wrsync_delaypipe(4), 94 .overflow_checking("ON"), 95 .underflow_checking("ON"), 96 .use_eab("ON"), 97 .write_aclr_synch("OFF")) fifo_uwt ( 98 .aclr(1'b0), 99 .data({uwt_flag3, uwt_peak3[11:0]}), 100 .rdclk(clk), 101 .rdreq((~int_rdempty) & int_rdreq), 102 .wrclk(adc_clk), 103 .wrreq(~wrfull[1]), 104 .q(int_uwt_q), 105 .rdempty(), 106 .wrfull(wrfull[1]), 38 .wrfull(int_wrfull), 107 39 .rdfull(), 108 40 .rdusedw(), … … 116 48 begin 117 49 int_rdreq <= 1'b1; 118 int_ ready <= 1'b0;50 int_data_ready <= 1'b0; 119 51 state <= 1'b1; 120 52 end … … 124 56 if (~int_rdempty) 125 57 begin 126 int_raw_data <= int_raw_q; 127 int_uwt_data <= int_uwt_q; 58 int_data <= int_q; 128 59 int_rdreq <= 1'b0; 129 int_ ready <= 1'b1;60 int_data_ready <= 1'b1; 130 61 state <= 1'b0; 131 62 end … … 135 66 begin 136 67 int_rdreq <= 1'b1; 137 int_ ready <= 1'b0;68 int_data_ready <= 1'b0; 138 69 state <= 1'b1; 139 70 end … … 141 72 end 142 73 143 assign ready = int_ready; 144 assign raw_data = int_raw_data; 145 assign uwt_data = int_uwt_data; 74 assign data_ready = int_data_ready; 75 assign data = int_data; 146 76 147 77 endmodule -
trunk/MultiChannelUSB/adc_lvds.v
r63 r72 7 7 input wire lvds_dco, 8 8 input wire lvds_fco, 9 input wire [ 2:0]lvds_d,9 input wire [size-1:0] lvds_d, 10 10 11 11 output wire [size*width-1:0] adc_data … … 61 61 62 62 generate 63 for (j = 1; j < size; j = j + 1)63 for (j = 0; j < size; j = j + 1) 64 64 begin : ADC_LVDS_OUTPUT 65 65 assign adc_data[j*width+width-1:j*width] = int_adc_data[j]; -
trunk/MultiChannelUSB/analyser.v
r50 r72 5 5 input wire [1:0] uwt_flag, 6 6 input wire [11:0] uwt_data, 7 input wire [11:0] threshold,8 7 output wire peak_ready, 9 8 output wire [11:0] peak … … 14 13 reg peak_ready_reg, peak_ready_next; 15 14 reg [11:0] peak_reg, peak_next; 16 reg [15:0] buffer [15:0];17 wire [15:0] sample;18 wire [11:0] baseline;19 15 20 integer i;21 22 assign sample = {4'd0, uwt_data};23 assign baseline = buffer[15][15:4];24 25 16 always @(posedge clk) 26 17 begin … … 31 22 peak_ready_reg <= 1'b0; 32 23 peak_reg <= 12'd0; 33 34 for(i = 0; i <= 15; i = i + 1)35 begin36 buffer[i] <= 12'd0;37 end38 24 end 39 25 else … … 42 28 counter_reg <= counter_next; 43 29 peak_ready_reg <= peak_ready_next; 44 peak_reg <= peak_next; 45 46 if (data_ready & uwt_flag[1]) 47 begin 48 for(i = 0; i < 15; i = i + 1) 49 begin 50 buffer[i+1] <= buffer[i] + sample; 51 end 52 buffer[0] <= sample; 53 end 30 peak_reg <= peak_next; 54 31 end 55 32 end … … 92 69 if (data_ready & uwt_flag[0]) 93 70 begin 94 peak_next = (uwt_data > baseline) ? (uwt_data - baseline) : 12'd0;95 peak_ready_next = (peak_next > threshold);71 peak_next = uwt_data; 72 peak_ready_next = 1'b1; 96 73 end 97 74 else -
trunk/MultiChannelUSB/control.v
r69 r72 2 2 ( 3 3 input wire clk, 4 5 output wire cfg_reset, 6 input wire [15:0] cfg_src_data, 7 output wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr, 8 4 9 input wire rx_empty, tx_full, 5 10 input wire [7:0] rx_data, … … 44 49 reg int_i2c_wrreq; 45 50 51 reg int_cfg_reset; 52 reg [15:0] int_dst_data, int_dst_addr; 46 53 47 54 wire crc_error = 1'b0; … … 54 61 wire [15:0] src, dst; 55 62 56 reg [15:0] memory [15:0];57 63 reg [7:0] buffer [7:0]; 58 64 59 assign src = (buffer[0][7]) ? memory[buffer[3][3:0]]: {buffer[2], buffer[3]};65 assign src = (buffer[0][7]) ? cfg_src_data : {buffer[2], buffer[3]}; 60 66 assign dst = {1'b0, buffer[0][6:0], buffer[1]}; 61 67 … … 113 119 idle_counter <= 5'd0; 114 120 byte_counter <= 3'd0; 121 int_cfg_reset <= 1'b0; 115 122 state <= 5'd1; 116 123 end … … 147 154 if (~crc_error) 148 155 begin 149 memory[dst[3:0]] <= src; 156 int_dst_addr <= dst; 157 int_dst_data <= src; 158 // memory[dst[3:0]] <= src; 150 159 151 160 case (dst) 152 161 16'h0000: 153 162 begin 163 int_cfg_reset <= 1'b1; 154 164 state <= 5'd0; 155 165 end … … 187 197 int_i2c_wrreq <= 1'b1; 188 198 state <= 5'd15; 199 end 200 201 default: 202 begin 203 state <= 5'd0; 189 204 end 190 205 endcase … … 339 354 end 340 355 356 assign cfg_reset = int_cfg_reset; 357 assign cfg_src_addr = {buffer[2], buffer[3]}; 358 assign cfg_dst_data = int_dst_data; 359 assign cfg_dst_addr = int_dst_addr; 341 360 assign mux_reset = int_reset; 342 361 assign mux_type = int_type; -
trunk/MultiChannelUSB/histogram.v
r70 r72 1 1 module histogram 2 #( 3 parameter W = 32 // bin resolution 4 ) 2 5 ( 3 6 input wire clk, reset, 4 7 input wire data_ready, 5 8 input wire [11:0] data, address, 6 output wire [ 31:0] q9 output wire [W-1:0] q 7 10 ); 8 11 … … 12 15 reg wren_reg, wren_next; 13 16 reg [11:0] addr_reg, addr_next; 14 reg [ 31:0] data_reg, data_next;17 reg [W-1:0] data_reg, data_next; 15 18 16 wire [ 31:0] q_a_wire, q_b_wire;19 wire [W-1:0] q_a_wire, q_b_wire; 17 20 18 21 wire [11:0] addr_wire; 19 wire [ 31:0] data_wire;22 wire [W-1:0] data_wire; 20 23 21 24 assign addr_wire = (flag_reg) ? data : addr_reg; … … 42 45 .widthad_a(12), 43 46 .widthad_b(12), 44 .width_a( 32),45 .width_b( 32),47 .width_a(W), 48 .width_b(W), 46 49 .width_byteena_a(1), 47 50 .width_byteena_b(1), -
trunk/MultiChannelUSB/oscilloscope.v
r52 r72 2 2 ( 3 3 input wire clk, reset, 4 input wire data_ready, 5 input wire [15:0] raw_data, uwt_data, threshold,4 input wire data_ready, trigger, 5 input wire [15:0] data, 6 6 input wire [9:0] address, 7 7 output wire [9:0] start_address, … … 24 24 wire [15:0] data_wire; 25 25 26 assign data_wire = (flag_reg) ? raw_data : data_reg;26 assign data_wire = (flag_reg) ? data : data_reg; 27 27 28 28 altsyncram #( … … 159 159 state_next = 4'd2; 160 160 161 if ((~trig_reg) 162 & (counter_reg == 10'd512) 163 & (uwt_data >= threshold)) 161 if ((~trig_reg) & (trigger) 162 & (counter_reg == 10'd512)) 164 163 begin 165 164 // trigger -
trunk/MultiChannelUSB/uwt_bior31.v
r27 r72 5 5 ( 6 6 input wire clk, reset, 7 input wire data_ready, 7 8 input wire [31:0] x, 8 9 output wire [31:0] d, … … 30 31 integer i; 31 32 32 always @(posedge clk , posedge reset)33 always @(posedge clk) 33 34 begin 34 35 if (reset) … … 44 45 end 45 46 end 46 else 47 else if (data_ready) 47 48 begin 48 49 d_reg <= d_next;
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