Changeset 72 for trunk/MultiChannelUSB/Paella.v
- Timestamp:
- Nov 25, 2009, 11:02:29 PM (15 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/Paella.v (modified) (9 diffs)
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trunk/MultiChannelUSB/Paella.v
r70 r72 6 6 inout wire [3:0] TRG, 7 7 inout wire I2C_SDA, 8 output wire I2C_SCL,8 inout wire I2C_SCL, 9 9 inout wire [4:0] CON_A, 10 10 inout wire [15:0] CON_B, … … 43 43 ); 44 44 45 localparam N = 3; 46 45 47 // Turn output ports off 46 48 /* … … 105 107 ); 106 108 107 reg ana_reset [3:0]; 108 wire ana_peak_ready [3:0]; 109 wire [11:0] ana_peak [3:0]; 110 111 reg osc_reset [3:0]; 112 reg [9:0] osc_addr [3:0]; 113 wire [9:0] osc_start_addr [3:0]; 114 wire [15:0] osc_q [3:0]; 115 116 reg hst_reset [3:0]; 117 reg [11:0] hst_addr [3:0]; 118 wire [31:0] hst_q [3:0]; 109 reg bln_reset [N-1:0]; 110 wire [11:0] baseline [N-1:0]; 111 wire [11:0] bln_baseline [N-1:0]; 112 113 reg ana_reset [N-1:0]; 114 wire ana_peak_ready [N-1:0]; 115 wire [11:0] ana_peak [N-1:0]; 116 117 reg osc_reset [N-1:0]; 118 reg [9:0] osc_addr [N-1:0]; 119 wire [9:0] osc_start_addr [N-1:0]; 120 wire [15:0] osc_q [N-1:0]; 121 wire osc_trig [N-1:0]; 122 123 wire [3:0] osc_mux_sel [N-1:0]; 124 wire [11:0] osc_mux_data [N-1:0]; 125 126 wire trg_reset [N-1:0]; 127 wire [3:0] trg_mux_sel [N-1:0]; 128 wire [11:0] trg_mux_data [N-1:0]; 129 wire [11:0] trg_thrs [N-1:0]; 130 131 reg hst_reset [N-1:0]; 132 reg [11:0] hst_addr [N-1:0]; 133 wire hst_data_ready [N-1:0]; 134 wire [11:0] hst_data [N-1:0]; 135 wire [31:0] hst_q [N-1:0]; 136 137 138 wire [3:0] hst_mux_sel [N-1:0]; 139 wire [12:0] hst_mux_data [N-1:0]; 140 141 wire [3:0] bln_mux_sel [N-1:0]; 142 wire [11:0] bln_mux_data [N-1:0]; 119 143 120 144 wire mux_reset, mux_type; … … 126 150 reg [15:0] mux_min_addr, mux_max_addr; 127 151 128 wire adc_clk [3:0]; 129 wire adc_data_ready [3:0]; 130 wire [11:0] adc_data [3:0]; 131 132 wire [11:0] raw_data [3:0]; 133 wire [11:0] uwt_data [3:0]; 134 wire [1:0] uwt_flag [3:0]; 152 wire adc_clk [N-1:0]; 153 wire [11:0] adc_data [N-1:0]; 154 155 wire data_ready [N-1:0]; 156 wire [11:0] data [N-1:0]; 157 wire [11:0] int_data [N-1:0]; 135 158 136 wire [16:0] osc_thrs [3:0]; 137 wire adc_pola [3:0]; 138 159 /* 139 160 assign osc_thrs[0] = 16'd40; 140 161 assign osc_thrs[1] = 16'd60; 141 162 assign osc_thrs[2] = 16'd40; 142 163 assign osc_thrs[3] = 16'd1650; 143 144 assign adc_pola[0] = 1'b1; 145 assign adc_pola[1] = 1'b1; 146 assign adc_pola[2] = 1'b1; 147 assign adc_pola[3] = 1'b0; 164 */ 165 wire [31:0] uwt_d1 [N-1:0]; 166 wire [31:0] uwt_a1 [N-1:0]; 167 wire [31:0] uwt_peak1 [N-1:0]; 168 wire [31:0] uwt_d2 [N-1:0]; 169 wire [31:0] uwt_a2 [N-1:0]; 170 wire [31:0] uwt_peak2 [N-1:0]; 171 wire [31:0] uwt_d3 [N-1:0]; 172 wire [31:0] uwt_a3 [N-1:0]; 173 wire [31:0] uwt_peak3 [N-1:0]; 174 175 wire [1:0] uwt_flag1 [N-1:0]; 176 wire [1:0] uwt_flag2 [N-1:0]; 177 wire [1:0] uwt_flag3 [N-1:0]; 148 178 149 179 assign adc_clk[0] = ADC_FCO; 150 180 assign adc_clk[1] = ADC_FCO; 151 181 // assign adc_clk[2] = ADC_FCO; 152 182 /* 153 183 assign adc_clk[3] = ADC_FCO; 184 */ 154 185 /* 155 186 assign adc_clk[3] = CON_CCLK[0]; … … 196 227 .sdoin()); 197 228 */ 198 /* 229 199 230 adc_lvds #( 200 .size( 3),231 .size(2), 201 232 .width(12)) adc_lvds_unit ( 202 233 .lvds_dco(ADC_DCO), 203 234 // .lvds_dco(adc_pll_clk), 204 235 .lvds_fco(ADC_FCO), 205 .lvds_d(ADC_D), 206 .adc_data({ adc_data[0], 207 adc_data[1], 208 adc_data[2] })); 209 */ 236 .lvds_d(ADC_D[1:0]), 237 .adc_data({ adc_data[1], 238 adc_data[0] })); 239 240 241 reg [15:0] cfg_memory [31:0]; 242 wire [15:0] cfg_src_data; 243 wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr; 244 245 wire cfg_polarity [N-1:0]; 246 wire [11:0] cfg_baseline [N-1:0]; 247 wire [11:0] cfg_hst_threshold [N-1:0]; 248 wire [11:0] cfg_trg_threshold [N-1:0]; 249 250 wire cfg_reset; 251 252 integer j; 253 254 always @(posedge CLK_50MHz) 255 begin 256 if (cfg_reset) 257 begin 258 for(j = 0; j <= 31; j = j + 1) 259 begin 260 cfg_memory[j] <= 16'd0; 261 end 262 end 263 else 264 begin 265 cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data; 266 end 267 end 268 210 269 genvar i; 270 211 271 generate 212 for (i = 0; i < 3; i = i + 1)272 for (i = 0; i < N; i = i + 1) 213 273 begin : MCA_CHAIN 274 275 assign cfg_polarity[i] = cfg_memory[10][4*i]; 276 assign cfg_baseline[i] = cfg_memory[11+i][11:0]; 277 assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0]; 278 assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0]; 279 280 assign osc_mux_sel[i] = cfg_memory[20+i][3:0]; 281 assign trg_mux_sel[i] = cfg_memory[20+i][7:4]; 282 assign hst_mux_sel[i] = cfg_memory[20+i][11:8]; 283 assign bln_mux_sel[i] = cfg_memory[20+i][15:12]; 284 214 285 adc_fifo adc_fifo_unit ( 215 286 .adc_clk(adc_clk[i]), 216 287 .adc_data(adc_data[i]), 217 .polarity(adc_pola[i]), 218 .clk(CLK_50MHz), 219 .ready(adc_data_ready[i]), 220 .raw_data(raw_data[i]), 221 .uwt_data({uwt_flag[i], uwt_data[i]})); 288 .clk(CLK_50MHz), 289 .data_ready(data_ready[i]), 290 .data(int_data[i])); 291 292 assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]); 293 294 uwt_bior31 #(.L(1)) uwt_1_unit ( 295 .clk(CLK_50MHz), 296 .data_ready(data_ready[i]), 297 .x({20'h00000, data[i]}), 298 .d(uwt_d1[i]), 299 .a(uwt_a1[i]), 300 .peak(uwt_peak1[i]), 301 .flag(uwt_flag1[i])); 302 303 uwt_bior31 #(.L(2)) uwt_2_unit ( 304 .clk(CLK_50MHz), 305 .data_ready(data_ready[i]), 306 .x(uwt_a1[i]), 307 .d(uwt_d2[i]), 308 .a(uwt_a2[i]), 309 .peak(uwt_peak2[i]), 310 .flag(uwt_flag2[i])); 311 312 uwt_bior31 #(.L(3)) uwt_3_unit ( 313 .clk(CLK_50MHz), 314 .data_ready(data_ready[i]), 315 .x(uwt_a2[i]), 316 .d(uwt_d3[i]), 317 .a(uwt_a3[i]), 318 .peak(uwt_peak3[i]), 319 .flag(uwt_flag3[i])); 320 321 lpm_mux #( 322 .lpm_size(4), 323 .lpm_type("LPM_MUX"), 324 .lpm_width(12), 325 .lpm_widths(2)) osc_mux_unit ( 326 .sel(osc_mux_sel[i][1:0]), 327 .data({ uwt_a3[i][20:9], 328 uwt_a2[i][17:6], 329 uwt_a1[i][14:3], 330 data[i] }), 331 .result(osc_mux_data[i])); 332 333 lpm_mux #( 334 .lpm_size(4), 335 .lpm_type("LPM_MUX"), 336 .lpm_width(12), 337 .lpm_widths(2)) trg_mux_unit ( 338 .sel(trg_mux_sel[i][1:0]), 339 .data({ uwt_a3[i][20:9], 340 uwt_a2[i][17:6], 341 uwt_a1[i][14:3], 342 data[i] }), 343 .result(trg_mux_data[i])); 344 345 lpm_mux #( 346 .lpm_size(2), 347 .lpm_type("LPM_MUX"), 348 .lpm_width(13), 349 .lpm_widths(1)) hst_mux_unit ( 350 .sel(hst_mux_sel[i][0]), 351 .data({ {ana_peak[i], ana_peak_ready[i]}, 352 {data[i], data_ready[i]} }), 353 .result(hst_mux_data[i])); 222 354 355 lpm_mux #( 356 .lpm_size(2), 357 .lpm_type("LPM_MUX"), 358 .lpm_width(12), 359 .lpm_widths(1)) bln_mux_unit ( 360 .sel(bln_mux_sel[i][0]), 361 .data({bln_baseline[i], cfg_baseline[i]}), 362 .result(bln_mux_data[i])); 363 364 baseline baseline_unit ( 365 .clk(CLK_50MHz), 366 .reset(bln_reset[i]), 367 .data_ready(data_ready[i]), 368 .uwt_flag(uwt_flag3[i]), 369 .uwt_data(uwt_peak3[i]), 370 .baseline(bln_baseline[i])); 371 223 372 analyser analyser_unit ( 224 373 .clk(CLK_50MHz), 225 374 .reset(ana_reset[i]), 226 .data_ready(adc_data_ready[i]), 227 .uwt_flag(uwt_flag[i]), 228 .uwt_data(uwt_data[i]), 229 .threshold(12'd10), 375 .data_ready(data_ready[i]), 376 .uwt_flag(uwt_flag3[i]), 377 .uwt_data(uwt_peak3[i]), 230 378 .peak_ready(ana_peak_ready[i]), 231 379 .peak(ana_peak[i])); 232 380 233 histogram histogram_unit ( 381 assign hst_data[i] = (hst_mux_data[i][12:1] > bln_mux_data[i]) ? (hst_mux_data[i][12:1] - bln_mux_data[i]) : 12'd0; 382 assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]); 383 384 histogram #(.W(32)) histogram_unit ( 234 385 .clk(CLK_50MHz), 235 386 .reset(hst_reset[i]), 236 .data_ready(adc_data_ready[i]), 237 .data(raw_data[i]), 238 // .data(uwt_data[i]), 387 .data_ready(hst_data_ready[i]), 388 .data(hst_data[i]), 239 389 .address(hst_addr[i]), 240 390 .q(hst_q[i])); 241 /* 242 histogram histogram_unit ( 243 .clk(CLK_50MHz), 244 .reset(hst_reset[i]), 245 .data_ready(ana_peak_ready[i]), 246 .data(ana_peak[i]), 247 .address(hst_addr[i]), 248 .q(hst_q[i])); 249 */ 391 392 trigger trigger_unit ( 393 .clk(CLK_50MHz), 394 .reset(trg_reset[i]), 395 .data_ready(data_ready[i]), 396 .data(trg_mux_data[i]), 397 .threshold(cfg_trg_threshold[i]), 398 .trigger(osc_trig[i])); 399 400 250 401 oscilloscope oscilloscope_unit ( 251 402 .clk(CLK_50MHz), 252 403 .reset(osc_reset[i]), 253 .data_ready(adc_data_ready[i]), 254 .raw_data(raw_data[i]), 255 .uwt_data(uwt_data[i]), 256 .threshold(osc_thrs[i]), 404 .data_ready(data_ready[i]), 405 .data(osc_mux_data[i]), 406 .trigger(osc_trig[i]), 257 407 .address(osc_addr[i]), 258 408 .start_address(osc_start_addr[i]), … … 261 411 endgenerate 262 412 263 integer j;264 265 413 always @* 266 414 begin 267 for (j = 0; j < 4; j = j + 1)415 for (j = 0; j < N; j = j + 1) 268 416 begin 269 417 osc_reset[j] = 1'b0; … … 273 421 end 274 422 275 case({mux_type, mux_chan}) 276 3'b000, 3'b001, 3'b010, 3'b011: 423 case(mux_type) 424 // case({mux_type, mux_chan}) 425 1'b0: 426 // 3'b000, 3'b001, 3'b010, 3'b011: 277 427 begin 278 428 osc_reset[mux_chan] = mux_reset; … … 283 433 end 284 434 285 3'b100, 3'b101, 3'b110, 3'b111: 435 1'b1: 436 // 3'b100, 3'b101, 3'b110, 3'b011: 286 437 begin 287 438 hst_reset[mux_chan] = mux_reset; … … 332 483 control control_unit ( 333 484 .clk(CLK_50MHz), 485 .cfg_reset(cfg_reset), 486 .cfg_src_data(cfg_memory[cfg_src_addr[4:0]]), 487 .cfg_src_addr(cfg_src_addr), 488 .cfg_dst_data(cfg_dst_data), 489 .cfg_dst_addr(cfg_dst_addr), 334 490 .rx_empty(usb_rx_empty), 335 491 .tx_full(usb_tx_full),
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