source: trunk/MultiChannelUSB

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Added
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Diff Rev Age Author Log Message
(edit) @81   15 years demin activate all 3 ADC channels
(edit) @80   15 years demin simplify analyser interface
(edit) @79   15 years demin switch from 8 to 4 byte command
(edit) @78   15 years demin make configuration frame always visible
(edit) @77   15 years demin add configuration form and activate all channels
(edit) @76   15 years demin add counter between peaks
(edit) @75   15 years demin fix osc_mux and trg_mux
(edit) @74   15 years demin fix signal shape display configuration
(edit) @73   15 years demin first working version
(edit) @72   15 years demin testing all components together
(edit) @71   15 years demin move to central clock domain
(edit) @70   15 years demin intermediate working version with 32 bit histograms, test block and …
(edit) @69   15 years demin add I2C master
(edit) @68   15 years demin add I2C master and switch from 24 to 32 bit histogram
(edit) @67   15 years demin switch from 24 to 32 bit histogram
(edit) @66   15 years demin first working version
(edit) @65   15 years demin start testing SRAM
(edit) @64   15 years demin switch eab on
(edit) @63   15 years demin add parameters for number of channels and channel resolution
(edit) @62   15 years demin add polarity flag
(edit) @61   15 years demin add interface for parallel ADC with unreliable clock
(edit) @60   15 years demin interface for parallel ADC with unreliable clock
(edit) @59   15 years demin move control and test code to separate modules
(edit) @58   15 years demin code cleanup
(edit) @57   15 years demin switch to direct instantiation of altsyncram and dcfifo
(edit) @56   15 years demin switch to direct instantiation of altsyncram
(edit) @55   15 years demin add pll for lvds interface
(edit) @54   15 years demin adapat memory access to normal memory clock
(edit) @53   15 years demin add signal invertor
(edit) @52   15 years demin switch to normal memory clock
(edit) @51   15 years demin first attempt to use normal memory clock
(edit) @50   15 years demin fix peak detection logic and add peak threshold
(edit) @49   15 years demin add registers for output data
(edit) @48   15 years demin cleanup test circuit
(edit) @47   15 years demin switch to direct instantiation of altsyncram
(edit) @46   15 years demin use loop for addr and reset initialisation
(edit) @45   15 years demin add fourth channel and switch from 32 to 24 bit histogram
(edit) @44   15 years demin add baseline subtraction
(edit) @43   15 years demin put back lost PIN_98 and PIN_99
(edit) @42   15 years demin code cleanup
(edit) @41   15 years demin add one real ADC channel
(edit) @39   15 years demin add configuration for EPCS16
(edit) @38   15 years demin add serial flash loader
(edit) @37   15 years demin fix communication with fifo_rx_unit
(edit) @36   15 years demin several minor fixes
(edit) @35   15 years demin first working version
(edit) @34   15 years demin working test version
(edit) @33   15 years demin return to simple USB interface with some adjustments
(edit) @31   15 years demin attemp to improve USB interface
(edit) @30   15 years demin put all components in place
(edit) @29   15 years demin split USB_PA into separate wires
(add) @27   15 years demin initial commit
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