Changeset 59 for trunk/MultiChannelUSB
- Timestamp:
- Sep 18, 2009, 1:40:49 PM (15 years ago)
- Location:
- trunk/MultiChannelUSB
- Files:
-
- 3 added
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/MultiChannelUSB/Paella.v
r54 r59 66 66 assign USB_PA6 = ~usb_pktend; 67 67 68 reg led_reg;69 assign LED = led_reg;70 71 68 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend; 72 wire usb_fifo_aclr; 73 reg usb_fifo_tx_wrreq; 74 reg usb_fifo_rx_rdreq; 75 wire usb_fifo_tx_full, usb_fifo_rx_empty; 76 reg [7:0] usb_fifo_tx_data; 77 wire [7:0] usb_fifo_rx_data; 69 wire usb_aclr; 70 wire usb_tx_wrreq, usb_rx_rdreq; 71 wire usb_tx_full, usb_rx_empty; 72 wire [7:0] usb_tx_data, usb_rx_data; 78 73 wire [1:0] usb_addr; 79 74 … … 81 76 assign USB_SLWR = ~usb_wrreq; 82 77 83 usb_fifo usb_ fifo_unit78 usb_fifo usb_unit 84 79 ( 85 80 .usb_clk(USB_IFCLK), … … 94 89 95 90 .clk(CLK_50MHz), 96 .aclr(usb_ fifo_aclr),97 98 .tx_full(usb_ fifo_tx_full),99 .tx_wrreq( (~usb_fifo_tx_full) & usb_fifo_tx_wrreq),100 .tx_data(usb_ fifo_tx_data),101 102 .rx_empty(usb_ fifo_rx_empty),103 .rx_rdreq( (~usb_fifo_rx_empty) & usb_fifo_rx_rdreq),104 .rx_q(usb_ fifo_rx_data)91 .aclr(usb_aclr), 92 93 .tx_full(usb_tx_full), 94 .tx_wrreq(usb_tx_wrreq), 95 .tx_data(usb_tx_data), 96 97 .rx_empty(usb_rx_empty), 98 .rx_rdreq(usb_rx_rdreq), 99 .rx_q(usb_rx_data) 105 100 ); 106 101 107 reg [23:0] rx_counter;108 reg [10:0] tst_counter;109 110 102 reg ana_reset [3:0]; 111 103 wire ana_peak_ready [3:0]; … … 113 105 114 106 reg osc_reset [3:0]; 107 reg [9:0] osc_addr [3:0]; 115 108 wire [9:0] osc_start_addr [3:0]; 116 reg [9:0] osc_addr [3:0];117 109 wire [15:0] osc_q [3:0]; 118 reg [15:0] osc_q_mux;119 110 120 111 reg hst_reset [3:0]; … … 122 113 wire [23:0] hst_q [3:0]; 123 114 124 reg mux_reset, mux_type; 125 reg [1:0] mux_chan, mux_byte, mux_max_byte; 126 reg [15:0] mux_addr, mux_min_addr, mux_max_addr, mux_num_addr; 115 wire mux_reset, mux_type; 116 wire [1:0] mux_chan, mux_byte; 117 wire [15:0] mux_addr; 118 127 119 reg [7:0] mux_q; 128 129 reg [3:0] state1, state2; 130 reg adc_fifo_aclr; 120 reg [1:0] mux_max_byte; 121 reg [15:0] mux_min_addr, mux_max_addr; 131 122 132 123 wire adc_clk [3:0]; 133 134 135 124 wire adc_data_ready [3:0]; 136 125 wire [11:0] adc_data [3:0]; … … 146 135 assign adc_clk[3] = CON_B[0]; 147 136 assign adc_data[3] = CON_B[12:1]; 148 137 /* 149 138 wire adc_pll_clk; 150 139 151 wire tst_adc_clk;152 reg [11:0] tst_adc_data;153 /*154 assign adc_clk[3] = tst_adc_clk;155 assign adc_data[3] = tst_adc_data;156 */157 /*158 140 adc_pll adc_pll_unit( 159 141 .inclk0(ADC_FCO), 160 142 .c0(adc_pll_clk)); 161 143 */ 162 163 pll pll_unit( 144 /* 145 wire tst_adc_clk; 146 wire [11:0] tst_adc_data; 147 148 test test_unit( 164 149 .inclk0(CLK_50MHz), 165 .c0(tst_adc_clk)); 166 150 .tst_clk(tst_adc_clk), 151 .tst_data(tst_adc_data)); 152 153 assign adc_clk[3] = tst_adc_clk; 154 assign adc_data[3] = tst_adc_data; 155 */ 167 156 /* 168 157 altserial_flash_loader #( … … 184 173 .lvds_fco(ADC_FCO), 185 174 .lvds_d(ADC_D), 186 .adc_db(adc_data[ 0]),175 .adc_db(adc_data[2]), 187 176 .adc_dc(adc_data[1]), 188 .adc_dd(adc_data[ 2]));177 .adc_dd(adc_data[0])); 189 178 190 179 genvar i; 191 180 generate 192 for (i = 0; i < 4; i = i + 1)181 for (i = 2; i < 4; i = i + 1) 193 182 begin : MCA_CHAIN 194 183 adc_fifo adc_fifo_unit ( 195 184 .adc_clk(adc_clk[i]), 196 185 .adc_data(adc_data[i]), 197 .aclr(adc_fifo_aclr), 198 .rdclk(CLK_50MHz), 186 .clk(CLK_50MHz), 199 187 .ready(adc_data_ready[i]), 200 188 .raw_data(raw_data[i]), … … 253 241 end 254 242 255 case({mux_type, mux_chan})243 case({mux_type, mux_chan}) 256 244 3'b000, 3'b001, 3'b010, 3'b011: 257 245 begin … … 260 248 mux_max_byte = 2'd1; 261 249 mux_min_addr = {6'd0, osc_start_addr[mux_chan]}; 262 mux_ num_addr = 16'd1023;250 mux_max_addr = 16'd1023; 263 251 end 264 252 … … 269 257 mux_max_byte = 2'd2; 270 258 mux_min_addr = 16'd0; 271 mux_ num_addr = 16'd4095;259 mux_max_addr = 16'd4095; 272 260 end 273 261 endcase … … 276 264 always @* 277 265 begin 278 case ({mux_type, mux_byte})279 5'b000: mux_q = osc_q[mux_chan][7:0];280 5'b001: mux_q = osc_q[mux_chan][15:8];281 282 5'b100: mux_q = hst_q[mux_chan][7:0];283 5'b101: mux_q = hst_q[mux_chan][15:8];284 5'b110: mux_q = hst_q[mux_chan][23:16];266 case ({mux_type, mux_byte}) 267 3'b000: mux_q = osc_q[mux_chan][7:0]; 268 3'b001: mux_q = osc_q[mux_chan][15:8]; 269 270 3'b100: mux_q = hst_q[mux_chan][7:0]; 271 3'b101: mux_q = hst_q[mux_chan][15:8]; 272 3'b110: mux_q = hst_q[mux_chan][23:16]; 285 273 286 274 default: mux_q = 8'd0; … … 288 276 end 289 277 290 291 always @(posedge CLK_50MHz) 292 begin 293 if (~usb_fifo_rx_empty) 294 begin 295 led_reg <= 1'b0; 296 rx_counter <= 24'd0; 297 end 298 else 299 begin 300 if (&rx_counter) 301 begin 302 led_reg <= 1'b1; 303 end 304 else 305 begin 306 rx_counter <= rx_counter + 24'd1; 307 end 308 end 309 310 case(state1) 311 1: 312 begin 313 usb_fifo_rx_rdreq <= 1'b1; 314 usb_fifo_tx_wrreq <= 1'b0; 315 mux_type <= 1'b0; 316 mux_chan <= 2'd0; 317 mux_byte <= 2'd0; 318 mux_reset <= 1'b0; 319 state1 <= 4'd2; 320 end 321 322 2: 323 begin 324 if (~usb_fifo_rx_empty) 325 begin 326 case (usb_fifo_rx_data) 327 8'h40, 8'h41, 8'h42, 8'h43, 8'h50, 8'h51, 8'h52, 8'h53: 328 begin 329 usb_fifo_rx_rdreq <= 1'b0; 330 mux_type <= usb_fifo_rx_data[4]; 331 mux_chan <= usb_fifo_rx_data[1:0]; 332 mux_reset <= 1'b1; 333 state1 <= 4'd1; 334 end 335 336 8'h60, 8'h61, 8'h62, 8'h63, 8'h70, 8'h71, 8'h72, 8'h73: 337 begin 338 usb_fifo_rx_rdreq <= 1'b0; 339 mux_type <= usb_fifo_rx_data[4]; 340 mux_chan <= usb_fifo_rx_data[1:0]; 341 state1 <= 4'd3; 342 end 343 344 8'h30: 345 begin 346 usb_fifo_rx_rdreq <= 1'b0; 347 state1 <= 4'd1; 348 end 349 350 8'h31: 351 begin 352 usb_fifo_rx_rdreq <= 1'b0; 353 tst_counter <= 11'd0; 354 state1 <= 4'd6; 355 end 356 endcase 357 end 358 end 359 // mux transfer 360 3: 361 begin 362 mux_addr <= mux_min_addr; 363 mux_max_addr <= mux_min_addr + mux_num_addr; 364 mux_byte <= 2'd0; 365 state1 <= 4'd4; 366 end 367 368 4: 369 begin 370 usb_fifo_tx_wrreq <= 1'b0; 371 state1 <= 4'd5; 372 end 373 374 5: 375 begin 376 if (~usb_fifo_tx_full) 377 begin 378 usb_fifo_tx_data <= mux_q; 379 usb_fifo_tx_wrreq <= 1'b1; 380 if ((mux_byte == mux_max_byte) && (mux_addr == mux_max_addr)) 381 begin 382 state1 <= 4'd1; 383 end 384 else 385 begin 386 state1 <= 4'd4; 387 if (mux_byte == mux_max_byte) 388 begin 389 mux_addr <= mux_addr + 16'd1; 390 mux_byte <= 2'd0; 391 end 392 else 393 begin 394 mux_byte <= mux_byte + 2'd1; 395 end 396 end 397 end 398 end 399 400 // tst transfer 401 6: 402 begin 403 usb_fifo_tx_data <= tst_counter; 404 usb_fifo_tx_wrreq <= 1'b1; 405 tst_counter <= tst_counter + 11'd1; 406 state1 <= 4'd8; 407 end 408 7: 409 begin 410 if (~usb_fifo_tx_full) 411 begin 412 usb_fifo_tx_data <= tst_counter; 413 if (tst_counter == 11'd0) 414 begin 415 state1 <= 4'd9; 416 end 417 else 418 begin 419 tst_counter <= tst_counter + 11'd1; 420 end 421 end 422 end 423 8: 424 begin 425 if (~usb_fifo_tx_full) 426 begin 427 usb_fifo_tx_wrreq <= 1'b0; 428 state1 <= 4'd1; 429 end 430 end 431 432 default: 433 begin 434 state1 <= 4'd1; 435 end 436 endcase 437 end 438 439 always @ (posedge tst_adc_clk) 440 begin 441 case (state2) 442 1: 443 begin 444 tst_adc_data <= 12'd0; 445 state2 <= 4'd2; 446 end 447 448 2: 449 begin 450 tst_adc_data <= 12'd1024; 451 state2 <= 4'd3; 452 end 453 454 3: 455 begin 456 tst_adc_data <= 12'd2048; 457 state2 <= 4'd4; 458 end 459 460 4: 461 begin 462 tst_adc_data <= 12'd3072; 463 state2 <= 4'd5; 464 end 465 466 5: 467 begin 468 tst_adc_data <= 12'd4095; 469 state2 <= 4'd1; 470 end 471 472 default: 473 begin 474 state2 <= 4'd1; 475 end 476 endcase 477 end 278 control control_unit ( 279 .clk(CLK_50MHz), 280 .rx_empty(usb_rx_empty), 281 .tx_full(usb_tx_full), 282 .rx_data(usb_rx_data), 283 .mux_max_byte(mux_max_byte), 284 .mux_min_addr(mux_min_addr), 285 .mux_max_addr(mux_max_addr), 286 .mux_q(mux_q), 287 .mux_reset(mux_reset), 288 .mux_type(mux_type), 289 .mux_chan(mux_chan), 290 .mux_byte(mux_byte), 291 .mux_addr(mux_addr), 292 .rx_rdreq(usb_rx_rdreq), 293 .tx_wrreq(usb_tx_wrreq), 294 .tx_data(usb_tx_data), 295 .led(LED)); 478 296 479 297 endmodule
Note:
See TracChangeset
for help on using the changeset viewer.