Changeset 84 for trunk/MultiChannelUSB
- Timestamp:
- Dec 21, 2009, 5:09:06 PM (15 years ago)
- Location:
- trunk/MultiChannelUSB
- Files:
-
- 2 added
- 11 edited
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Paella.qsf (modified) (2 diffs)
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Paella.v (modified) (26 diffs)
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adc_fifo.v (modified) (4 diffs)
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analyser.v (modified) (5 diffs)
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control.v (modified) (15 diffs)
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histogram.v (modified) (11 diffs)
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i2c_fifo.v (modified) (3 diffs)
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oscilloscope.v (modified) (12 diffs)
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suppression.v (added)
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sys_pll.v (added)
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test.v (modified) (2 diffs)
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usb_fifo.v (modified) (2 diffs)
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uwt_bior31.v (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/MultiChannelUSB/Paella.qsf
r72 r84 59 59 set_global_assignment -name VERILOG_FILE histogram.v 60 60 set_global_assignment -name VERILOG_FILE trigger.v 61 set_global_assignment -name VERILOG_FILE suppression.v 61 62 set_global_assignment -name VERILOG_FILE oscilloscope.v 62 63 set_global_assignment -name VERILOG_FILE usb_fifo.v … … 65 66 set_global_assignment -name VERILOG_FILE test.v 66 67 set_global_assignment -name VERILOG_FILE test_pll.v 68 set_global_assignment -name VERILOG_FILE sys_pll.v 67 69 set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF 68 70 set_global_assignment -name ENABLE_CLOCK_LATENCY ON -
trunk/MultiChannelUSB/Paella.v
r81 r84 8 8 inout wire I2C_SCL, 9 9 inout wire [4:0] CON_A, 10 in out wire [15:0] CON_B,10 input wire [15:0] CON_B, 11 11 input wire [12:0] CON_C, 12 12 input wire [1:0] CON_BCLK, … … 52 52 assign RAM_ADDR = 20'h00000; 53 53 */ 54 assign RAM_CLK = CLK_50MHz;54 assign RAM_CLK = sys_clk; 55 55 assign RAM_CE1 = 1'b0; 56 56 … … 58 58 assign TRG = 4'bz; 59 59 assign CON_A = 5'bz; 60 assign CON_B = 16'bz;61 60 assign USB_PA0 = 1'bz; 62 61 assign USB_PA1 = 1'bz; … … 95 94 .usb_addr(usb_addr), 96 95 97 .clk( CLK_50MHz),96 .clk(sys_clk), 98 97 .aclr(usb_aclr), 99 98 … … 106 105 .rx_q(usb_rx_data) 107 106 ); 108 107 109 108 reg bln_reset [N-1:0]; 110 109 wire [11:0] baseline [N-1:0]; … … 113 112 reg ana_reset [N-1:0]; 114 113 wire ana_peak_ready [N-1:0]; 114 wire ana_peak_debug [N-1:0]; 115 115 116 116 reg osc_reset [N-1:0]; … … 155 155 wire [11:0] data [N-1:0]; 156 156 wire [11:0] int_data [N-1:0]; 157 158 wire cmp_data_ready; 159 wire [11:0] cmp_data; 160 161 wire ept_data_ready; 162 wire [47:0] ept_data; 157 163 164 wire [11:0] nowhere; 165 166 wire sys_clk; 167 168 158 169 /* 159 170 assign osc_thrs[0] = 16'd40; … … 176 187 wire [1:0] uwt_flag3 [N-1:0]; 177 188 178 179 180 189 assign adc_clk[0] = ADC_FCO; 190 assign adc_clk[1] = ADC_FCO; 191 assign adc_clk[2] = ADC_FCO; 181 192 182 193 /* … … 199 210 .c0(adc_pll_clk)); 200 211 */ 201 /* 202 wire tst_adc_clk; 203 wire [11:0] tst_adc_data; 212 213 sys_pll sys_pll_unit( 214 .inclk0(CLK_50MHz), 215 .c0(sys_clk)); 204 216 205 217 test test_unit( 206 .clk(CLK_50MHz), 207 .tst_clk(tst_adc_clk), 208 .tst_data(tst_adc_data)); 209 210 assign adc_clk[2] = tst_adc_clk; 211 assign adc_data[2] = tst_adc_data; 212 */ 213 /* 214 altserial_flash_loader #( 215 .enable_shared_access("OFF"), 216 .enhanced_mode(1), 217 .intended_device_family("Cyclone III")) sfl_unit ( 218 .noe(1'b0), 219 .asmi_access_granted(), 220 .asmi_access_request(), 221 .data0out(), 222 .dclkin(), 223 .scein(), 224 .sdoin()); 225 */ 218 .clk(ADC_FCO), 219 .data(adc_data[2])); 220 // .data(nowhere); 221 226 222 227 223 adc_lvds #( … … 232 228 .lvds_fco(ADC_FCO), 233 229 .lvds_d(ADC_D[2:0]), 234 .adc_data({ adc_data[2], 230 // .adc_data({ adc_data[2], 231 .adc_data({ nowhere, 235 232 adc_data[1], 236 233 adc_data[0] })); … … 250 247 integer j; 251 248 252 always @(posedge CLK_50MHz)249 always @(posedge sys_clk) 253 250 begin 254 251 if (cfg_reset) … … 265 262 end 266 263 264 assign ept_data_ready = cmp_data_ready & data_ready[2] & data_ready[1] & data_ready[0]; 265 assign ept_data = {cmp_data, int_data[2], int_data[1], int_data[0]}; 266 267 adc_fifo cmp_fifo_unit ( 268 .adc_clk(ADC_FCO), 269 .adc_data(CON_B[11:0]), 270 .clk(sys_clk), 271 .data_ready(cmp_data_ready), 272 .data(cmp_data)); 273 267 274 genvar i; 268 275 … … 285 292 .adc_clk(adc_clk[i]), 286 293 .adc_data(adc_data[i]), 287 .clk( CLK_50MHz),294 .clk(sys_clk), 288 295 .data_ready(data_ready[i]), 289 296 .data(int_data[i])); … … 292 299 293 300 uwt_bior31 #(.L(1)) uwt_1_unit ( 294 .clk( CLK_50MHz),301 .clk(sys_clk), 295 302 .data_ready(data_ready[i]), 296 303 .x({20'h00000, data[i]}), … … 301 308 302 309 uwt_bior31 #(.L(2)) uwt_2_unit ( 303 .clk( CLK_50MHz),310 .clk(sys_clk), 304 311 .data_ready(data_ready[i]), 305 312 .x(uwt_a1[i]), … … 310 317 311 318 uwt_bior31 #(.L(3)) uwt_3_unit ( 312 .clk( CLK_50MHz),319 .clk(sys_clk), 313 320 .data_ready(data_ready[i]), 314 321 .x(uwt_a2[i]), … … 319 326 320 327 lpm_mux #( 321 .lpm_size( 5),328 .lpm_size(7), 322 329 .lpm_type("LPM_MUX"), 323 330 .lpm_width(12), 324 331 .lpm_widths(3)) osc_mux_unit ( 325 332 .sel(osc_mux_sel[i][2:0]), 326 .data({ bln_baseline[i], 333 .data({ {ana_peak_debug[i], 11'd0}, 334 hst_data[i], 335 // uwt_d3[i][11:0], 336 bln_baseline[i], 327 337 uwt_a3[i][20:9], 328 338 uwt_a2[i][17:6], … … 332 342 333 343 lpm_mux #( 334 .lpm_size( 5),344 .lpm_size(7), 335 345 .lpm_type("LPM_MUX"), 336 346 .lpm_width(12), 337 347 .lpm_widths(3)) trg_mux_unit ( 338 348 .sel(trg_mux_sel[i][2:0]), 339 .data({ bln_baseline[i], 349 .data({ {ana_peak_ready[i], 11'd0}, 350 hst_data[i], 351 // uwt_d3[i][11:0], 352 bln_baseline[i], 340 353 uwt_a3[i][20:9], 341 354 uwt_a2[i][17:6], … … 364 377 365 378 baseline baseline_unit ( 366 .clk( CLK_50MHz),379 .clk(sys_clk), 367 380 .reset(bln_reset[i]), 368 381 .data_ready(data_ready[i]), … … 372 385 373 386 analyser analyser_unit ( 374 .clk( CLK_50MHz),387 .clk(sys_clk), 375 388 .reset(ana_reset[i]), 376 389 .data_ready(data_ready[i]), 377 390 .uwt_flag(uwt_flag3[i]), 378 .peak_ready(ana_peak_ready[i])); 379 380 assign hst_data[i] = (hst_mux_data[i][12:1] > bln_mux_data[i]) ? (hst_mux_data[i][12:1] - bln_mux_data[i]) : 12'd0; 391 .peak_ready(ana_peak_ready[i]), 392 .peak_debug(ana_peak_debug[i])); 393 394 suppression suppression_unit ( 395 .clk(sys_clk), 396 .data(hst_mux_data[i][12:1]), 397 .baseline(bln_mux_data[i]), 398 .result(hst_data[i])); 399 381 400 assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]); 382 401 383 402 histogram #(.W(32)) histogram_unit ( 384 .clk( CLK_50MHz),403 .clk(sys_clk), 385 404 .reset(hst_reset[i]), 386 405 .data_ready(hst_data_ready[i]), … … 390 409 391 410 trigger trigger_unit ( 392 .clk( CLK_50MHz),411 .clk(sys_clk), 393 412 .reset(trg_reset[i]), 394 413 .data_ready(data_ready[i]), … … 399 418 400 419 oscilloscope oscilloscope_unit ( 401 .clk( CLK_50MHz),420 .clk(sys_clk), 402 421 .reset(osc_reset[i]), 403 422 .data_ready(data_ready[i]), … … 465 484 466 485 i2c_fifo i2c_unit( 467 .clk( CLK_50MHz),486 .clk(sys_clk), 468 487 .aclr(i2c_aclr), 469 488 .wrreq(i2c_wrreq), … … 481 500 482 501 control control_unit ( 483 .clk( CLK_50MHz),502 .clk(sys_clk), 484 503 .cfg_reset(cfg_reset), 485 504 .cfg_src_data(cfg_memory[cfg_src_addr[4:0]]), … … 505 524 .ram_addr(RAM_ADDR), 506 525 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}), 526 .ept_data_ready(ept_data_ready), 527 .ept_data(ept_data), 507 528 .i2c_wrreq(i2c_wrreq), 508 529 .i2c_data(i2c_data), … … 510 531 .led(LED)); 511 532 533 /* 534 altserial_flash_loader #( 535 .enable_shared_access("OFF"), 536 .enhanced_mode(1), 537 .intended_device_family("Cyclone III")) sfl_unit ( 538 .noe(1'b0), 539 .asmi_access_granted(), 540 .asmi_access_request(), 541 .data0out(), 542 .dclkin(), 543 .scein(), 544 .sdoin()); 545 */ 546 512 547 endmodule -
trunk/MultiChannelUSB/adc_fifo.v
r72 r84 12 12 reg [11:0] int_data; 13 13 14 reg state, int_rdreq, int_data_ready; 14 reg [1:0] state; 15 reg int_rdreq, int_data_ready; 15 16 wire int_wrfull, int_rdempty; 16 17 … … 26 27 .overflow_checking("ON"), 27 28 .underflow_checking("ON"), 28 .use_eab("O FF"),29 .use_eab("ON"), 29 30 .write_aclr_synch("OFF")) fifo_unit ( 30 31 .aclr(1'b0), … … 45 46 begin 46 47 case (state) 47 1'b0:48 2'd0: 48 49 begin 49 50 int_rdreq <= 1'b1; 50 51 int_data_ready <= 1'b0; 51 state <= 1'b1;52 state <= 2'd1; 52 53 end 53 54 54 1'b1:55 2'd1: 55 56 begin 56 57 if (~int_rdempty) … … 59 60 int_rdreq <= 1'b0; 60 61 int_data_ready <= 1'b1; 61 state <= 1'b0;62 state <= 2'd0; 62 63 end 63 64 end 64 65 65 default:66 2'd2: 66 67 begin 67 int_rdreq <= 1'b1;68 68 int_data_ready <= 1'b0; 69 state <= 1'b1;69 state <= 2'd3; 70 70 end 71 72 2'd3: 73 begin 74 state <= 2'd0; 75 end 76 71 77 endcase 72 78 end -
trunk/MultiChannelUSB/analyser.v
r76 r84 4 4 input wire data_ready, 5 5 input wire [1:0] uwt_flag, 6 output wire peak_ready 6 output wire peak_ready, 7 output wire peak_debug 7 8 ); 8 9 10 reg flag_reg, flag_next; 9 11 reg [1:0] state_reg, state_next; 10 reg [ 3:0] counter_reg, counter_next;11 reg peak_ready_reg , peak_ready_next;12 reg [4:0] counter_reg, counter_next; 13 reg peak_ready_reg; 12 14 13 15 wire counter_max = (&counter_reg); 16 wire peak_ready_int = (flag_reg & data_ready & uwt_flag[0] & counter_max); 14 17 15 18 always @(posedge clk) … … 17 20 if (reset) 18 21 begin 22 flag_reg <= 1'b0; 19 23 state_reg <= 2'd0; 20 counter_reg <= 4'd0;24 counter_reg <= 5'd0; 21 25 peak_ready_reg <= 1'b0; 22 26 end 23 27 else 24 28 begin 29 flag_reg <= flag_next; 25 30 state_reg <= state_next; 26 31 counter_reg <= counter_next; 27 peak_ready_reg <= peak_ready_ next;32 peak_ready_reg <= peak_ready_int; 28 33 end 29 34 end … … 31 36 always @* 32 37 begin 38 flag_next = flag_reg; 33 39 state_next = state_reg; 34 40 counter_next = counter_reg; 35 peak_ready_next = peak_ready_reg;36 41 case (state_reg) 37 42 0: // skip first 16 samples 38 43 begin 39 peak_ready_next = 1'b0;44 flag_next = 1'b0; 40 45 if (data_ready) 41 46 begin 42 counter_next = counter_reg + 4'd1;47 counter_next = counter_reg + 5'd1; 43 48 if (counter_max) 44 49 begin … … 50 55 1: // skip first 16 minima 51 56 begin 57 flag_next = 1'b0; 52 58 if (data_ready & uwt_flag[1]) 53 59 begin 54 counter_next = counter_reg + 4'd1;60 counter_next = counter_reg + 5'd1; 55 61 if (counter_max) 56 62 begin … … 62 68 2: 63 69 begin 64 if (data_ready & uwt_flag[0] & counter_max) 70 flag_next = 1'b1; 71 if (data_ready) 65 72 begin 66 counter_next = 4'd0;67 peak_ready_next = 1'b1;68 end69 else70 begin71 73 if (~counter_max) 72 74 begin 73 counter_next = counter_reg + 4'd1;75 counter_next = counter_reg + 5'd1; 74 76 end 75 peak_ready_next = 1'b0; 76 end 77 if (peak_ready_int) 78 begin 79 counter_next = 5'd0; 80 end 81 end 77 82 end 78 83 79 84 default: 80 85 begin 86 flag_next = 1'b0; 81 87 state_next = 2'd0; 82 counter_next = 4'd0; 83 peak_ready_next = 1'b0; 88 counter_next = 5'd0; 84 89 end 85 90 endcase 86 91 end 87 92 88 assign peak_ready = peak_ready_reg; 93 assign peak_ready = peak_ready_int; 94 assign peak_debug = peak_ready_reg; 89 95 endmodule -
trunk/MultiChannelUSB/control.v
r79 r84 28 28 inout wire [17:0] ram_data, 29 29 30 input wire ept_data_ready, 31 input wire [47:0] ept_data, 32 30 33 output wire i2c_wrreq, 31 34 output wire [15:0] i2c_data, … … 36 39 37 40 reg [23:0] led_counter; 38 reg [1 8:0] ram_counter;41 reg [19:0] ram_counter; 39 42 reg [10:0] tst_counter; 40 43 reg [15:0] int_addr, int_max_addr; … … 49 52 reg int_i2c_wrreq; 50 53 54 reg [47:0] int_ept_data; 55 51 56 reg int_cfg_reset; 52 57 reg [15:0] int_dst_data, int_dst_addr; … … 74 79 // assign ram_data = int_ram_we ? int_ram_data : 18'bz; 75 80 // assign ram_addr = {ram_counter[18:5],1'd0,ram_counter[4:0]}; 76 assign ram_addr = {1'd0, ram_counter[18:0]};81 assign ram_addr = ram_counter; 77 82 78 83 genvar j; … … 116 121 int_ram_we <= 1'b0; 117 122 int_ram_data <= 16'd0; 118 ram_counter <= 19'd0;123 ram_counter <= 20'd0; 119 124 idle_counter <= 5'd0; 120 125 byte_counter <= 2'd0; … … 183 188 begin 184 189 tst_counter <= 11'd0; 185 state <= 5'd 6;190 state <= 5'd7; 186 191 end 187 192 16'h0004: … … 189 194 int_ram_we <= 1'b1; 190 195 int_ram_data <= 18'd0; 191 ram_counter <= 19'd0;192 state <= 5'd 9;196 ram_counter <= 20'd0; 197 state <= 5'd10; 193 198 end 194 199 16'h0005: … … 196 201 int_i2c_data <= src; 197 202 int_i2c_wrreq <= 1'b1; 198 state <= 5'd15; 203 state <= 5'd16; 204 end 205 16'h0006: 206 begin 207 int_ram_we <= 1'b1; 208 int_ram_data <= 18'd0; 209 ram_counter <= 20'd0; 210 state <= 5'd17; 199 211 end 200 212 … … 226 238 5: 227 239 begin 240 state <= 5'd6; 241 end 242 243 6: 244 begin 228 245 if (~tx_full) 229 246 begin … … 251 268 252 269 // tst transfer 253 6:270 7: 254 271 begin 255 272 crc_reset <= 1'b0; … … 257 274 int_wrreq <= 1'b1; 258 275 tst_counter <= tst_counter + 11'd1; 259 state <= 5'd 7;260 end 261 7:276 state <= 5'd8; 277 end 278 8: 262 279 begin 263 280 if (~tx_full) … … 266 283 if (&tst_counter) 267 284 begin 268 state <= 5'd 8;285 state <= 5'd9; 269 286 end 270 287 else … … 274 291 end 275 292 end 276 8:293 9: 277 294 begin 278 295 if (~tx_full) … … 283 300 end 284 301 // ram transfer 285 9:302 10: 286 303 begin 287 304 crc_reset <= 1'b0; 288 state <= 5'd1 0;289 end 290 1 0:305 state <= 5'd11; 306 end 307 11: 291 308 begin 292 309 int_ram_data[8:1] <= ram_counter[7:0]; 293 310 // int_ram_data[8:1] <= 8'd0; 294 if (&ram_counter )295 begin 296 state <= 5'd1 1;311 if (&ram_counter[18:0]) 312 begin 313 state <= 5'd12; 297 314 end 298 315 else 299 316 begin 300 state <= 5'd 9;301 ram_counter <= ram_counter + 19'd1;302 end 303 end 304 1 1:317 state <= 5'd10; 318 ram_counter <= ram_counter + 20'd1; 319 end 320 end 321 12: 305 322 begin 306 323 int_ram_we <= 1'b0; 307 324 int_ram_data <= 18'd0; 308 ram_counter <= 19'd0;309 state <= 5'd1 2;310 end 311 1 2:325 ram_counter <= 20'd0; 326 state <= 5'd13; 327 end 328 13: 312 329 begin 313 330 int_wrreq <= 1'b0; 314 state <= 5'd13;315 end316 13:317 begin318 331 state <= 5'd14; 319 332 end 320 333 14: 334 begin 335 state <= 5'd15; 336 end 337 15: 338 begin 339 if (~tx_full) 340 begin 341 int_data <= int_ram_q[8:1]; 342 int_wrreq <= 1'b1; 343 if (&ram_counter[18:0]) 344 begin 345 state <= 5'd0; 346 end 347 else 348 begin 349 state <= 5'd13; 350 ram_counter <= ram_counter + 20'd1; 351 end 352 end 353 end 354 355 // i2c write 356 16: 357 begin 358 crc_reset <= 1'b0; 359 if (~i2c_full) 360 begin 361 int_i2c_wrreq <= 1'b0; 362 state <= 5'd0; 363 end 364 end 365 366 // long sample transfer 367 17: 368 begin 369 crc_reset <= 1'b0; 370 if (ept_data_ready) 371 begin 372 ram_counter <= ram_counter + 20'd1; 373 int_ept_data <= ept_data; 374 state <= 5'd18; 375 end 376 end 377 18: 378 begin 379 // int_ram_data[8:1] <= ram_counter[7:0]; 380 int_ram_data[8:1] <= int_ept_data[7:0]; 381 int_ram_data[17:10] <= int_ept_data[15:8]; 382 ram_counter <= ram_counter + 20'd1; 383 state <= 5'd19; 384 end 385 19: 386 begin 387 // int_ram_data[8:1] <= ram_counter[7:0]; 388 int_ram_data[8:1] <= int_ept_data[23:16]; 389 int_ram_data[17:10] <= int_ept_data[31:24]; 390 ram_counter <= ram_counter + 20'd1; 391 state <= 5'd20; 392 end 393 394 20: 395 begin 396 // int_ram_data[8:1] <= ram_counter[7:0]; 397 int_ram_data[8:1] <= int_ept_data[39:32]; 398 int_ram_data[17:10] <= int_ept_data[47:40]; 399 if (&ram_counter) 400 begin 401 int_ram_we <= 1'b0; 402 int_ram_data <= 18'd0; 403 ram_counter <= 19'd0; 404 state <= 5'd21; 405 end 406 else 407 begin 408 state <= 5'd17; 409 end 410 end 411 /* 412 21: 413 begin 414 int_wrreq <= 1'b0; 415 state <= 5'd22; 416 end 417 418 22: 419 begin 420 state <= 5'd23; 421 end 422 423 23: 321 424 begin 322 425 if (~tx_full) … … 330 433 else 331 434 begin 332 state <= 5'd12; 333 ram_counter <= ram_counter + 19'd1; 334 end 335 end 336 end 337 338 // i2c write 339 15: 340 begin 341 crc_reset <= 1'b0; 342 if (~i2c_full) 343 begin 344 int_i2c_wrreq <= 1'b0; 345 state <= 5'd0; 435 state <= 5'd21; 436 ram_counter <= ram_counter + 20'd1; 437 end 438 end 439 end 440 */ 441 21: 442 begin 443 int_wrreq <= 1'b0; 444 state <= 5'd22; 445 end 446 447 22: 448 begin 449 state <= 5'd23; 450 end 451 452 23: 453 begin 454 if (~tx_full) 455 begin 456 int_data <= int_ram_q[8:1]; 457 int_wrreq <= 1'b1; 458 state <= 5'd24; 459 end 460 end 461 462 24: 463 begin 464 int_data <= int_ram_q[17:10]; 465 state <= 5'd25; 466 end 467 468 25: 469 begin 470 if (~tx_full) 471 begin 472 int_wrreq <= 1'b0; 473 if (&ram_counter) 474 begin 475 state <= 5'd0; 476 end 477 else 478 begin 479 state <= 5'd21; 480 ram_counter <= ram_counter + 20'd1; 481 end 346 482 end 347 483 end -
trunk/MultiChannelUSB/histogram.v
r72 r84 12 12 // signal declaration 13 13 reg [3:0] state_reg, state_next; 14 reg flag_reg, flag_next;15 14 reg wren_reg, wren_next; 16 15 reg [11:0] addr_reg, addr_next; … … 18 17 19 18 wire [W-1:0] q_a_wire, q_b_wire; 20 21 wire [11:0] addr_wire;22 wire [W-1:0] data_wire;23 24 assign addr_wire = (flag_reg) ? data : addr_reg;25 assign data_wire = (flag_reg) ? (q_a_wire + 32'd1) : data_reg;26 19 27 20 altsyncram #( … … 39 32 .outdata_aclr_a("NONE"), 40 33 .outdata_aclr_b("NONE"), 41 .outdata_reg_a(" UNREGISTERED"),42 .outdata_reg_b(" UNREGISTERED"),34 .outdata_reg_a("CLOCK0"), 35 .outdata_reg_b("CLOCK0"), 43 36 .power_up_uninitialized("FALSE"), 44 37 .read_during_write_mode_mixed_ports("OLD_DATA"), … … 53 46 .clock0(clk), 54 47 .wren_b(1'b0), 55 .address_a(addr_ wire),48 .address_a(addr_reg), 56 49 .address_b(address), 57 .data_a(data_ wire),50 .data_a(data_reg), 58 51 .data_b(), 59 52 .q_a(q_a_wire), … … 79 72 if (reset) 80 73 begin 81 flag_reg <= 1'b0;82 74 wren_reg <= 1'b1; 83 75 addr_reg <= 12'd0; … … 87 79 else 88 80 begin 89 flag_reg <= flag_next;90 81 wren_reg <= wren_next; 91 82 addr_reg <= addr_next; … … 97 88 always @* 98 89 begin 99 flag_next = flag_reg;100 90 wren_next = wren_reg; 101 91 addr_next = addr_reg; … … 106 96 begin 107 97 // nothing to do 108 flag_next = 1'b0;109 98 wren_next = 1'b0; 110 99 addr_next = 12'd0; … … 118 107 if (&addr_reg) 119 108 begin 120 flag_next = 1'b1;121 109 wren_next = 1'b0; 122 110 state_next = 4'd2; … … 130 118 2: 131 119 begin 120 wren_next = 1'b0; 132 121 if (data_ready) 133 122 begin 134 if (&q_a_wire) 135 begin 136 flag_next = 1'b0; 137 state_next = 4'd0; 138 end 139 else 140 begin 141 wren_next = 1'b1; 142 state_next = 4'd3; 143 end 123 addr_next = data; 124 state_next = 4'd3; 144 125 end 145 126 end … … 147 128 3: 148 129 begin 149 wren_next = 1'b0; 150 state_next = 4'd2; 130 state_next = 4'd4; 131 end 132 133 4: 134 begin 135 if (&q_a_wire) 136 begin 137 state_next = 4'd0; 138 end 139 else 140 begin 141 wren_next = 1'b1; 142 data_next = q_a_wire + 32'd1; 143 state_next = 4'd2; 144 end 151 145 end 152 146 153 147 default: 154 148 begin 155 flag_next = 1'b0;156 149 wren_next = 1'b0; 157 150 addr_next = 12'd0; -
trunk/MultiChannelUSB/i2c_fifo.v
r71 r84 15 15 reg int_rdreq, int_clken, int_sdo, int_scl, int_ack; 16 16 reg [15:0] int_data; 17 reg [ 8:0] counter;17 reg [9:0] counter; 18 18 reg [4:0] state; 19 19 20 20 assign i2c_sda = int_sdo ? 1'bz : 1'b0; 21 assign i2c_scl = int_scl | (int_clken ? counter[ 8] : 1'b0);21 assign i2c_scl = int_scl | (int_clken ? counter[9] : 1'b0); 22 22 23 23 assign start = int_data[8]; … … 34 34 .overflow_checking("ON"), 35 35 .underflow_checking("ON"), 36 .use_eab("O FF")) fifo_tx (36 .use_eab("ON")) fifo_tx ( 37 37 .rdreq((~int_rdempty) & (int_rdreq) & (&counter)), 38 38 .aclr(aclr), … … 50 50 always @ (posedge clk) 51 51 begin 52 counter <= counter + 9'd1;52 counter <= counter + 10'd1; 53 53 if (&counter) 54 54 begin -
trunk/MultiChannelUSB/oscilloscope.v
r72 r84 11 11 // signal declaration 12 12 reg [3:0] state_reg, state_next; 13 reg flag_reg, flag_next;14 13 reg wren_reg, wren_next; 15 14 reg [9:0] addr_reg, addr_next; … … 21 20 22 21 wire [15:0] q_wire; 23 24 wire [15:0] data_wire;25 26 assign data_wire = (flag_reg) ? data : data_reg;27 22 28 23 altsyncram #( … … 38 33 .operation_mode("DUAL_PORT"), 39 34 .outdata_aclr_b("NONE"), 40 .outdata_reg_b(" UNREGISTERED"),35 .outdata_reg_b("CLOCK0"), 41 36 .power_up_uninitialized("FALSE"), 42 37 .read_during_write_mode_mixed_ports("OLD_DATA"), … … 50 45 .address_a(addr_reg), 51 46 .address_b(address), 52 .data_a(data_ wire),47 .data_a(data_reg), 53 48 .q_b(q_wire), 54 49 .aclr0(1'b0), … … 76 71 begin 77 72 state_reg <= 4'b1; 78 flag_reg <= 1'b0;79 73 wren_reg <= 1'b1; 80 74 addr_reg <= 10'd0; … … 87 81 begin 88 82 state_reg <= state_next; 89 flag_reg <= flag_next;90 83 wren_reg <= wren_next; 91 84 addr_reg <= addr_next; … … 100 93 begin 101 94 state_next = state_reg; 102 flag_next = flag_reg;103 95 wren_next = wren_reg; 104 96 addr_next = addr_reg; … … 113 105 // nothing to do 114 106 state_next = 4'b0; 115 flag_next = 1'b0;116 107 wren_next = 1'b0; 117 108 addr_next = 10'd0; … … 125 116 if (&addr_reg) 126 117 begin 127 flag_next = 1'b1;128 118 wren_next = 1'b0; 129 119 state_next = 4'd2; … … 140 130 begin 141 131 wren_next = 1'b1; 132 data_next = data; 142 133 state_next = 4'd3; 143 134 end … … 152 143 if (&counter_reg) 153 144 begin 154 flag_next = 1'b0;155 145 state_next = 4'd0; 156 146 end … … 177 167 begin 178 168 state_next = 4'b0; 179 flag_next = 1'b0;180 169 wren_next = 1'b0; 181 170 addr_next = 10'd0; -
trunk/MultiChannelUSB/test.v
r59 r84 2 2 ( 3 3 input wire clk, 4 output wire tst_clk, 5 output wire [11:0] tst_data 4 output wire [11:0] data 6 5 ); 7 6 8 wire int_clk;9 7 reg [11:0] int_data; 10 reg [2:0] state; 11 12 test_pll test_pll_unit( 13 .inclk0(clk), 14 .c0(int_clk)); 15 16 always @(posedge int_clk) 8 reg [5:0] counter; 9 reg [5:0] state; 10 11 always @(posedge clk) 17 12 begin 18 13 case (state) 14 /* 19 15 0: 20 16 begin … … 46 42 state <= 3'd0; 47 43 end 44 */ 45 46 6'd0: 47 begin 48 int_data <= 12'h030; 49 state <= 6'd1; 50 end 51 52 6'd1: 53 begin 54 int_data <= 12'h034; 55 state <= 6'd2; 56 end 57 58 6'd2: 59 begin 60 int_data <= 12'h081; 61 state <= 6'd3; 62 end 63 64 6'd3: 65 begin 66 int_data <= 12'h0f5; 67 state <= 6'd4; 68 end 69 70 6'd4: 71 begin 72 int_data <= 12'h10a; 73 state <= 6'd5; 74 end 75 76 6'd5: 77 begin 78 int_data <= 12'h11a; 79 state <= 6'd6; 80 end 81 82 6'd6: 83 begin 84 int_data <= 12'h124; 85 state <= 6'd7; 86 end 87 88 6'd7: 89 begin 90 int_data <= 12'h124; 91 state <= 6'd8; 92 end 93 94 6'd8: 95 begin 96 int_data <= 12'h12b; 97 state <= 6'd9; 98 end 99 100 6'd9: 101 begin 102 int_data <= 12'h12a; 103 state <= 6'd10; 104 end 105 106 6'd10: 107 begin 108 int_data <= 12'h12a; 109 state <= 6'd11; 110 end 111 112 6'd11: 113 begin 114 int_data <= 12'h12b; 115 state <= 6'd12; 116 end 117 118 6'd12: 119 begin 120 int_data <= 12'h12a; 121 state <= 6'd13; 122 end 123 124 6'd13: 125 begin 126 int_data <= 12'h12e; 127 state <= 6'd14; 128 end 129 130 6'd14: 131 begin 132 int_data <= 12'h12b; 133 state <= 6'd15; 134 end 135 136 6'd15: 137 begin 138 int_data <= 12'h12b; 139 state <= 6'd16; 140 end 141 142 6'd16: 143 begin 144 int_data <= 12'h12e; 145 state <= 6'd17; 146 end 147 148 6'd17: 149 begin 150 int_data <= 12'h12b; 151 state <= 6'd18; 152 end 153 154 6'd18: 155 begin 156 int_data <= 12'h12a; 157 state <= 6'd19; 158 end 159 160 6'd19: 161 begin 162 int_data <= 12'h12e; 163 state <= 6'd20; 164 end 165 166 6'd20: 167 begin 168 int_data <= 12'h12b; 169 state <= 6'd21; 170 end 171 172 6'd21: 173 begin 174 int_data <= 12'h12e; 175 state <= 6'd22; 176 end 177 178 6'd22: 179 begin 180 int_data <= 12'h12f; 181 state <= 6'd23; 182 end 183 184 6'd23: 185 begin 186 int_data <= 12'h12f; 187 state <= 6'd24; 188 end 189 190 6'd24: 191 begin 192 int_data <= 12'h12b; 193 state <= 6'd25; 194 end 195 196 6'd25: 197 begin 198 int_data <= 12'h12b; 199 state <= 6'd26; 200 end 201 202 6'd26: 203 begin 204 int_data <= 12'h12b; 205 state <= 6'd27; 206 end 207 208 6'd27: 209 begin 210 int_data <= 12'h12e; 211 state <= 6'd28; 212 end 213 214 6'd28: 215 begin 216 int_data <= 12'h12e; 217 state <= 6'd29; 218 end 219 220 6'd29: 221 begin 222 int_data <= 12'h12e; 223 state <= 6'd30; 224 end 225 226 6'd30: 227 begin 228 int_data <= 12'h12e; 229 state <= 6'd31; 230 end 231 232 6'd31: 233 begin 234 int_data <= 12'h12b; 235 state <= 6'd32; 236 end 237 238 6'd32: 239 begin 240 int_data <= 12'h12b; 241 state <= 6'd33; 242 end 243 244 6'd33: 245 begin 246 int_data <= 12'h12b; 247 state <= 6'd34; 248 end 249 250 6'd34: 251 begin 252 int_data <= 12'h12e; 253 state <= 6'd35; 254 end 255 256 6'd35: 257 begin 258 int_data <= 12'h12e; 259 state <= 6'd36; 260 end 261 262 6'd36: 263 begin 264 int_data <= 12'h12e; 265 state <= 6'd37; 266 end 267 268 6'd37: 269 begin 270 int_data <= 12'h12e; 271 state <= 6'd38; 272 end 273 274 6'd38: 275 begin 276 int_data <= 12'h12f; 277 state <= 6'd39; 278 end 279 280 6'd39: 281 begin 282 int_data <= 12'h12b; 283 state <= 6'd40; 284 end 285 286 6'd40: 287 begin 288 int_data <= 12'h12e; 289 state <= 6'd41; 290 end 291 292 6'd41: 293 begin 294 int_data <= 12'h12f; 295 state <= 6'd42; 296 end 297 298 6'd42: 299 begin 300 int_data <= 12'h0fb; 301 state <= 6'd43; 302 end 303 304 6'd43: 305 begin 306 int_data <= 12'h07e; 307 state <= 6'd44; 308 end 309 310 6'd44: 311 begin 312 int_data <= 12'h070; 313 state <= 6'd45; 314 end 315 316 6'd45: 317 begin 318 int_data <= 12'h05a; 319 state <= 6'd46; 320 end 321 322 6'd46: 323 begin 324 int_data <= 12'h045; 325 state <= 6'd47; 326 end 327 328 6'd47: 329 begin 330 int_data <= 12'h03f; 331 state <= 6'd48; 332 end 333 334 6'd48: 335 begin 336 int_data <= 12'h03b; 337 state <= 6'd49; 338 end 339 340 6'd49: 341 begin 342 int_data <= 12'h034; 343 state <= 6'd50; 344 end 345 346 6'd50: 347 begin 348 int_data <= 12'h035; 349 state <= 6'd51; 350 end 351 352 6'd51: 353 begin 354 int_data <= 12'h034; 355 state <= 6'd52; 356 end 357 358 6'd52: 359 begin 360 int_data <= 12'h034; 361 state <= 6'd53; 362 end 363 364 6'd53: 365 begin 366 int_data <= 12'h030; 367 state <= 6'd54; 368 end 369 370 6'd54: 371 begin 372 int_data <= 12'h030; 373 counter <= counter + 6'd1; 374 if (&counter) 375 begin 376 state <= 6'd0; 377 end 378 end 48 379 49 380 default: 50 381 begin 51 state <= 3'd0;382 state <= 6'd0; 52 383 end 53 384 endcase 54 385 end 55 386 56 assign tst_clk = int_clk; 57 assign tst_data = int_data; 387 assign data = int_data; 58 388 59 389 endmodule -
trunk/MultiChannelUSB/usb_fifo.v
r58 r84 35 35 .overflow_checking("ON"), 36 36 .underflow_checking("ON"), 37 .use_eab("O FF"),37 .use_eab("ON"), 38 38 .write_aclr_synch("OFF")) fifo_tx ( 39 39 .aclr(aclr), … … 62 62 .overflow_checking("ON"), 63 63 .underflow_checking("ON"), 64 .use_eab("O FF"),64 .use_eab("ON"), 65 65 .write_aclr_synch("OFF")) fifo_rx ( 66 66 .aclr(aclr), -
trunk/MultiChannelUSB/uwt_bior31.v
r72 r84 16 16 localparam index2 = 2 << (L - 1); 17 17 localparam index3 = 3 << (L - 1); 18 localparam peak_index = (( 3 << (L - 1)) + 1) >>1;18 localparam peak_index = ((index3 + 1) >> 1) + 1; 19 19 localparam peak_shift = ((L - 1) << 1) + (L - 1); 20 20 localparam zero = 32'h80000000; … … 26 26 reg [31:0] a_reg, a_next; 27 27 reg [31:0] peak_reg, peak_next; 28 29 reg [31:0] tmp1_reg, tmp1_next; 30 reg [31:0] tmp2_reg, tmp2_next; 31 32 reg less_reg, less_next; 33 reg more_reg, more_next; 28 34 29 35 reg [1:0] flag_reg; … … 39 45 peak_reg <= 0; 40 46 flag_reg <= 0; 47 tmp1_reg <= 0; 48 tmp2_reg <= 0; 49 less_reg <= 1'b0; 50 more_reg <= 1'b0; 41 51 42 52 for(i = 0; i <= index3; i = i + 1) … … 51 61 peak_reg <= peak_next; 52 62 53 flag_reg[0] <= (d_reg > zero) & (d_next <= zero); 54 flag_reg[1] <= (d_reg < zero) & (d_next >= zero); 55 63 tmp1_reg <= tmp1_next; 64 tmp2_reg <= tmp2_next; 65 less_reg <= less_next; 66 more_reg <= more_next; 67 68 flag_reg[0] <= (more_reg) & (~more_next); 69 flag_reg[1] <= (less_reg) & (~less_next); 70 56 71 // Tapped delay line: shift one 57 72 for(i = 0; i < index3; i = i + 1) … … 70 85 // The coefficients are [1, 3, -3, -1] and [1, 3, 3, 1] 71 86 87 tmp1_next = tap[index3] + {tap[index2][30:0], 1'b0} + tap[index2]; 88 tmp2_next = {tap[index1][30:0], 1'b0} + tap[index1] + tap[0]; 89 90 d_next = zero - tmp1_reg + tmp2_reg; 91 a_next = tmp1_reg + tmp2_reg; 92 93 more_next = (d_reg > zero); 94 less_next = (d_reg < zero); 95 96 /* 72 97 d_next = zero - (tap[index3]) 73 98 - (tap[index2] << 1) - tap[index2] … … 76 101 77 102 a_next = (tap[index3]) 78 + (tap[index2] << 1)+ tap[index2]103 + {tap[index2] << 1} + tap[index2] 79 104 + (tap[index1] << 1) + tap[index1] 80 105 + (tap[0]); 81 106 */ 82 107 peak_next = (tap[peak_index] >> peak_shift); 83 108 end
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