Changeset 84 for trunk/MultiChannelUSB/test.v
- Timestamp:
- Dec 21, 2009, 5:09:06 PM (15 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/test.v
r59 r84 2 2 ( 3 3 input wire clk, 4 output wire tst_clk, 5 output wire [11:0] tst_data 4 output wire [11:0] data 6 5 ); 7 6 8 wire int_clk;9 7 reg [11:0] int_data; 10 reg [2:0] state; 11 12 test_pll test_pll_unit( 13 .inclk0(clk), 14 .c0(int_clk)); 15 16 always @(posedge int_clk) 8 reg [5:0] counter; 9 reg [5:0] state; 10 11 always @(posedge clk) 17 12 begin 18 13 case (state) 14 /* 19 15 0: 20 16 begin … … 46 42 state <= 3'd0; 47 43 end 44 */ 45 46 6'd0: 47 begin 48 int_data <= 12'h030; 49 state <= 6'd1; 50 end 51 52 6'd1: 53 begin 54 int_data <= 12'h034; 55 state <= 6'd2; 56 end 57 58 6'd2: 59 begin 60 int_data <= 12'h081; 61 state <= 6'd3; 62 end 63 64 6'd3: 65 begin 66 int_data <= 12'h0f5; 67 state <= 6'd4; 68 end 69 70 6'd4: 71 begin 72 int_data <= 12'h10a; 73 state <= 6'd5; 74 end 75 76 6'd5: 77 begin 78 int_data <= 12'h11a; 79 state <= 6'd6; 80 end 81 82 6'd6: 83 begin 84 int_data <= 12'h124; 85 state <= 6'd7; 86 end 87 88 6'd7: 89 begin 90 int_data <= 12'h124; 91 state <= 6'd8; 92 end 93 94 6'd8: 95 begin 96 int_data <= 12'h12b; 97 state <= 6'd9; 98 end 99 100 6'd9: 101 begin 102 int_data <= 12'h12a; 103 state <= 6'd10; 104 end 105 106 6'd10: 107 begin 108 int_data <= 12'h12a; 109 state <= 6'd11; 110 end 111 112 6'd11: 113 begin 114 int_data <= 12'h12b; 115 state <= 6'd12; 116 end 117 118 6'd12: 119 begin 120 int_data <= 12'h12a; 121 state <= 6'd13; 122 end 123 124 6'd13: 125 begin 126 int_data <= 12'h12e; 127 state <= 6'd14; 128 end 129 130 6'd14: 131 begin 132 int_data <= 12'h12b; 133 state <= 6'd15; 134 end 135 136 6'd15: 137 begin 138 int_data <= 12'h12b; 139 state <= 6'd16; 140 end 141 142 6'd16: 143 begin 144 int_data <= 12'h12e; 145 state <= 6'd17; 146 end 147 148 6'd17: 149 begin 150 int_data <= 12'h12b; 151 state <= 6'd18; 152 end 153 154 6'd18: 155 begin 156 int_data <= 12'h12a; 157 state <= 6'd19; 158 end 159 160 6'd19: 161 begin 162 int_data <= 12'h12e; 163 state <= 6'd20; 164 end 165 166 6'd20: 167 begin 168 int_data <= 12'h12b; 169 state <= 6'd21; 170 end 171 172 6'd21: 173 begin 174 int_data <= 12'h12e; 175 state <= 6'd22; 176 end 177 178 6'd22: 179 begin 180 int_data <= 12'h12f; 181 state <= 6'd23; 182 end 183 184 6'd23: 185 begin 186 int_data <= 12'h12f; 187 state <= 6'd24; 188 end 189 190 6'd24: 191 begin 192 int_data <= 12'h12b; 193 state <= 6'd25; 194 end 195 196 6'd25: 197 begin 198 int_data <= 12'h12b; 199 state <= 6'd26; 200 end 201 202 6'd26: 203 begin 204 int_data <= 12'h12b; 205 state <= 6'd27; 206 end 207 208 6'd27: 209 begin 210 int_data <= 12'h12e; 211 state <= 6'd28; 212 end 213 214 6'd28: 215 begin 216 int_data <= 12'h12e; 217 state <= 6'd29; 218 end 219 220 6'd29: 221 begin 222 int_data <= 12'h12e; 223 state <= 6'd30; 224 end 225 226 6'd30: 227 begin 228 int_data <= 12'h12e; 229 state <= 6'd31; 230 end 231 232 6'd31: 233 begin 234 int_data <= 12'h12b; 235 state <= 6'd32; 236 end 237 238 6'd32: 239 begin 240 int_data <= 12'h12b; 241 state <= 6'd33; 242 end 243 244 6'd33: 245 begin 246 int_data <= 12'h12b; 247 state <= 6'd34; 248 end 249 250 6'd34: 251 begin 252 int_data <= 12'h12e; 253 state <= 6'd35; 254 end 255 256 6'd35: 257 begin 258 int_data <= 12'h12e; 259 state <= 6'd36; 260 end 261 262 6'd36: 263 begin 264 int_data <= 12'h12e; 265 state <= 6'd37; 266 end 267 268 6'd37: 269 begin 270 int_data <= 12'h12e; 271 state <= 6'd38; 272 end 273 274 6'd38: 275 begin 276 int_data <= 12'h12f; 277 state <= 6'd39; 278 end 279 280 6'd39: 281 begin 282 int_data <= 12'h12b; 283 state <= 6'd40; 284 end 285 286 6'd40: 287 begin 288 int_data <= 12'h12e; 289 state <= 6'd41; 290 end 291 292 6'd41: 293 begin 294 int_data <= 12'h12f; 295 state <= 6'd42; 296 end 297 298 6'd42: 299 begin 300 int_data <= 12'h0fb; 301 state <= 6'd43; 302 end 303 304 6'd43: 305 begin 306 int_data <= 12'h07e; 307 state <= 6'd44; 308 end 309 310 6'd44: 311 begin 312 int_data <= 12'h070; 313 state <= 6'd45; 314 end 315 316 6'd45: 317 begin 318 int_data <= 12'h05a; 319 state <= 6'd46; 320 end 321 322 6'd46: 323 begin 324 int_data <= 12'h045; 325 state <= 6'd47; 326 end 327 328 6'd47: 329 begin 330 int_data <= 12'h03f; 331 state <= 6'd48; 332 end 333 334 6'd48: 335 begin 336 int_data <= 12'h03b; 337 state <= 6'd49; 338 end 339 340 6'd49: 341 begin 342 int_data <= 12'h034; 343 state <= 6'd50; 344 end 345 346 6'd50: 347 begin 348 int_data <= 12'h035; 349 state <= 6'd51; 350 end 351 352 6'd51: 353 begin 354 int_data <= 12'h034; 355 state <= 6'd52; 356 end 357 358 6'd52: 359 begin 360 int_data <= 12'h034; 361 state <= 6'd53; 362 end 363 364 6'd53: 365 begin 366 int_data <= 12'h030; 367 state <= 6'd54; 368 end 369 370 6'd54: 371 begin 372 int_data <= 12'h030; 373 counter <= counter + 6'd1; 374 if (&counter) 375 begin 376 state <= 6'd0; 377 end 378 end 48 379 49 380 default: 50 381 begin 51 state <= 3'd0;382 state <= 6'd0; 52 383 end 53 384 endcase 54 385 end 55 386 56 assign tst_clk = int_clk; 57 assign tst_data = int_data; 387 assign data = int_data; 58 388 59 389 endmodule
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