Changeset 84 for trunk/MultiChannelUSB/adc_fifo.v

Timestamp:

Dec 21, 2009, 5:09:06 PM (15 years ago)

Author:

demin

Message:

improve timings in all components

File:

• trunk/MultiChannelUSB/adc_fifo.v (modified) (4 diffs)

trunk/MultiChannelUSB/adc_fifo.v

@@ -12 +12 @@
         reg             [11:0]  int_data;
         
-        reg                             state, int_rdreq, int_data_ready;
+        reg             [1:0]   state;
+        reg                             int_rdreq, int_data_ready;
         wire                    int_wrfull, int_rdempty;
 
@@ -26 +27 @@
                 .overflow_checking("ON"),
                 .underflow_checking("ON"),
-                .use_eab("OFF"),
+                .use_eab("ON"),
                 .write_aclr_synch("OFF")) fifo_unit (
                 .aclr(1'b0),
@@ -45 +46 @@
         begin
                 case (state)
-                        1'b0:
+                        2'd0:
                         begin
                                 int_rdreq <= 1'b1;
                                 int_data_ready <= 1'b0;
-                                state <= 1'b1;
+                                state <= 2'd1;
                         end
 
-                        1'b1: 
+                        2'd1: 
                         begin
                                 if (~int_rdempty)
@@ -59 +60 @@
                                         int_rdreq <= 1'b0;
                                         int_data_ready <= 1'b1;
-                                        state <= 1'b0;
+                                        state <= 2'd0;
                                 end
                         end
 
-                        default:
+                        2'd2:
                         begin
-                                int_rdreq <= 1'b1;
                                 int_data_ready <= 1'b0;
-                                state <= 1'b1;
+                                state <= 2'd3;
                         end
+
+                        2'd3:
+                        begin
+                                state <= 2'd0;
+                        end
+
                 endcase
         end