Changeset 86 for trunk/MultiChannelUSB/adc_fifo.v

Timestamp:

Dec 21, 2009, 11:55:05 PM (15 years ago)

Author:

demin

Message:

replace 3 ADC FIFO with one large FIFO

File:

• trunk/MultiChannelUSB/adc_fifo.v (modified) (4 diffs)

trunk/MultiChannelUSB/adc_fifo.v

@@ -1 +1 @@
 module adc_fifo
+        #(
+                parameter       W       =       48 // fifo width
+        )
         (
                 input   wire                    adc_clk,
-                input   wire    [11:0]  adc_data,
+                input   wire    [W-1:0] adc_data,
 
                 input   wire                    clk,
                 output  wire                    data_ready,
-                output  wire    [11:0]  data
+                output  wire    [W-1:0] data
         );
 
-        wire    [11:0]  int_q;
-        reg             [11:0]  int_data;
+        wire    [W-1:0] int_q;
+        reg             [W-1:0] int_data;
         
-        reg             [1:0]   state;
-        reg                             int_rdreq, int_data_ready;
+        reg                             state, int_rdreq, int_data_ready;
         wire                    int_wrfull, int_rdempty;
 
@@ -21 +23 @@
                 .lpm_showahead("ON"),
                 .lpm_type("dcfifo"),
-                .lpm_width(12),
+                .lpm_width(W),
                 .lpm_widthu(4),
                 .rdsync_delaypipe(4),
@@ -46 +48 @@
         begin
                 case (state)
-                        2'd0:
+                        1'b0:
                         begin
                                 int_rdreq <= 1'b1;
                                 int_data_ready <= 1'b0;
-                                state <= 2'd1;
+                                state <= 1'b1;
                         end
 
-                        2'd1: 
+                        1'b1: 
                         begin
                                 if (~int_rdempty)
@@ -60 +62 @@
                                         int_rdreq <= 1'b0;
                                         int_data_ready <= 1'b1;
-                                        state <= 2'd0;
+                                        state <= 1'b0;
                                 end
                         end
-
-                        2'd2:
-                        begin
-                                int_data_ready <= 1'b0;
-                                state <= 2'd3;
-                        end
-
-                        2'd3:
-                        begin
-                                state <= 2'd0;
-                        end
-
                 endcase
         end