Changeset 90 for trunk/MultiChannelUSB/adc_fifo.v
- Timestamp:
- Feb 27, 2010, 10:10:19 PM (15 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/adc_fifo.v
r86 r90 7 7 input wire [W-1:0] adc_data, 8 8 9 input wire clk,10 output wire data_ready,11 output wire [W-1:0] data9 input wire sys_clk, 10 output wire sys_good, 11 output wire [W-1:0] sys_data 12 12 ); 13 13 … … 15 15 reg [W-1:0] int_data; 16 16 17 reg state, int_rdreq, int_ data_ready;17 reg state, int_rdreq, int_good; 18 18 wire int_wrfull, int_rdempty; 19 19 … … 33 33 .aclr(1'b0), 34 34 .data(adc_data), 35 .rdclk( clk),35 .rdclk(sys_clk), 36 36 .rdreq((~int_rdempty) & int_rdreq), 37 37 .wrclk(adc_clk), … … 45 45 .wrusedw()); 46 46 47 always @(posedge clk)47 always @(posedge sys_clk) 48 48 begin 49 49 case (state) … … 51 51 begin 52 52 int_rdreq <= 1'b1; 53 int_ data_ready<= 1'b0;53 int_good <= 1'b0; 54 54 state <= 1'b1; 55 55 end … … 61 61 int_data <= int_q; 62 62 int_rdreq <= 1'b0; 63 int_ data_ready<= 1'b1;63 int_good <= 1'b1; 64 64 state <= 1'b0; 65 65 end … … 68 68 end 69 69 70 assign data_ready = int_data_ready;71 assign data = int_data;70 assign sys_good = int_good; 71 assign sys_data = int_data; 72 72 73 73 endmodule
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