Changeset 90
- Timestamp:
- Feb 27, 2010, 10:10:19 PM (15 years ago)
- Location:
- trunk/MultiChannelUSB
- Files:
-
- 1 added
- 3 deleted
- 11 edited
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Paella.qsf (modified) (1 diff)
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Paella.v (modified) (9 diffs)
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adc_fifo.v (modified) (7 diffs)
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analyser.v (modified) (2 diffs)
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baseline.v (deleted)
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configuration.v (added)
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control.v (modified) (8 diffs)
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histogram.v (modified) (9 diffs)
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i2c_fifo.v (modified) (5 diffs)
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oscilloscope.v (modified) (1 diff)
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pll.v (deleted)
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suppression.v (deleted)
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trigger.v (modified) (1 diff)
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usb_fifo.v (modified) (3 diffs)
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uwt_bior31.v (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/MultiChannelUSB/Paella.qsf
r84 r90 56 56 set_global_assignment -name VERILOG_FILE control.v 57 57 set_global_assignment -name VERILOG_FILE analyser.v 58 set_global_assignment -name VERILOG_FILE baseline.v59 58 set_global_assignment -name VERILOG_FILE histogram.v 60 59 set_global_assignment -name VERILOG_FILE trigger.v 61 set_global_assignment -name VERILOG_FILE suppression.v62 60 set_global_assignment -name VERILOG_FILE oscilloscope.v 61 set_global_assignment -name VERILOG_FILE configuration.v 63 62 set_global_assignment -name VERILOG_FILE usb_fifo.v 64 63 set_global_assignment -name VERILOG_FILE i2c_fifo.v -
trunk/MultiChannelUSB/Paella.v
r86 r90 52 52 assign RAM_ADDR = 20'h00000; 53 53 */ 54 assign RAM_CLK = sys_cl k;54 assign RAM_CLK = sys_clock; 55 55 assign RAM_CE1 = 1'b0; 56 56 … … 73 73 74 74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend; 75 wire usb_aclr;76 75 wire usb_tx_wrreq, usb_rx_rdreq; 77 76 wire usb_tx_full, usb_rx_empty; … … 94 93 .usb_addr(usb_addr), 95 94 96 .clk(sys_clk), 97 .aclr(usb_aclr), 95 .clk(sys_clock), 98 96 99 97 .tx_full(usb_tx_full), … … 106 104 ); 107 105 108 reg bln_reset [N-1:0]; 109 wire [11:0] baseline [N-1:0]; 110 wire [11:0] bln_baseline [N-1:0]; 111 112 reg ana_reset [N-1:0]; 113 wire ana_peak_ready [N-1:0]; 114 wire ana_peak_debug [N-1:0]; 115 116 reg osc_reset [N-1:0]; 117 reg [9:0] osc_addr [N-1:0]; 118 wire [9:0] osc_start_addr [N-1:0]; 119 wire [15:0] osc_q [N-1:0]; 120 wire osc_trig [N-1:0]; 121 122 wire [3:0] osc_mux_sel [N-1:0]; 106 wire ana_good [N-1:0]; 107 wire [11:0] ana_data [N-1:0]; 108 wire [11:0] ana_base [N-1:0]; 109 123 110 wire [11:0] osc_mux_data [N-1:0]; 124 111 125 wire trg_reset [N-1:0]; 126 wire [3:0] trg_mux_sel [N-1:0]; 127 wire [11:0] trg_mux_data [N-1:0]; 128 wire [11:0] trg_thrs [N-1:0]; 129 130 reg hst_reset [N-1:0]; 131 reg [11:0] hst_addr [N-1:0]; 132 wire hst_data_ready [N-1:0]; 133 wire [11:0] hst_data [N-1:0]; 134 wire [31:0] hst_q [N-1:0]; 135 136 137 wire [3:0] hst_mux_sel [N-1:0]; 138 wire [12:0] hst_mux_data [N-1:0]; 139 140 wire [3:0] bln_mux_sel [N-1:0]; 141 wire [11:0] bln_mux_data [N-1:0]; 142 143 wire mux_reset, mux_type; 144 wire [1:0] mux_chan, mux_byte; 145 wire [15:0] mux_addr; 146 147 reg [7:0] mux_q; 148 reg [1:0] mux_max_byte; 149 reg [15:0] mux_min_addr, mux_max_addr; 112 wire [11:0] trg_mux_data; 113 wire trg_flag; 114 115 wire [83:0] int_mux_data [N-1:0]; 116 117 wire sys_clock, sys_frame; 150 118 151 119 wire [11:0] adc_data [N-1:0]; 152 153 wire data_ready;154 wire [11:0] data [N-1:0];155 120 wire [11:0] int_data [N-1:0]; 156 157 121 wire [11:0] cmp_data; 158 159 122 wire [11:0] nowhere; 160 161 wire sys_clk;162 123 163 124 wire [31:0] uwt_d1 [N-1:0]; … … 174 135 wire [1:0] uwt_flag2 [N-1:0]; 175 136 wire [1:0] uwt_flag3 [N-1:0]; 137 138 wire i2c_reset; 176 139 177 140 /* … … 179 142 .lvds_dco(ADC_DCO), 180 143 .lvds_fco(ADC_FCO), 181 .para_ data_ready(CON_CCLK[0]),144 .para_good(CON_CCLK[0]), 182 145 .para_data(CON_C[11:0]), 183 146 .adc_data(adc_data[2])); … … 191 154 */ 192 155 193 sys_pll sys_pll_unit(194 .inclk0(CLK_50MHz),195 .c0(sys_clk));196 197 156 test test_unit( 198 157 .clk(ADC_FCO), 199 .data(adc_data[2]));200 // .data(nowhere);158 // .data(adc_data[2])); 159 .data(nowhere)); 201 160 202 161 adc_lvds #( … … 207 166 .lvds_fco(ADC_FCO), 208 167 .lvds_d(ADC_D[2:0]), 209 //.adc_data({ adc_data[2],210 .adc_data({ nowhere,168 .adc_data({ adc_data[2], 169 // .adc_data({ nowhere, 211 170 adc_data[1], 212 171 adc_data[0] })); 213 214 reg [15:0] cfg_memory [31:0];215 wire [15:0] cfg_src_data;216 wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr;217 218 wire cfg_polarity [N-1:0];219 wire [ 11:0] cfg_baseline [N-1:0];220 wire [11:0] cfg_hst_threshold [N-1:0]; 221 wire [ 11:0] cfg_trg_threshold [N-1:0];172 173 assign cmp_data = CON_B[11:0]; 174 assign sys_clock = ADC_DCO; 175 assign sys_frame = ADC_FCO; 176 177 wire [15:0] cfg_bits [15:0]; 178 wire [255:0] int_cfg_bits; 179 180 wire [31:0] cfg_mux_selector; 222 181 223 182 wire cfg_reset; 224 183 225 integer j; 226 227 always @(posedge sys_clk) 228 begin 229 if (cfg_reset) 230 begin 231 for(j = 0; j <= 31; j = j + 1) 232 begin 233 cfg_memory[j] <= 16'd0; 234 end 184 wire [7:0] bus_ssel; 185 wire bus_wren; 186 wire [31:0] bus_addr; 187 wire [15:0] bus_mosi; 188 wire [15:0] bus_miso [5:0]; 189 wire [5:0] bus_busy; 190 191 wire [15:0] mrg_bus_miso; 192 wire mrg_bus_busy; 193 194 wire [79:0] int_bus_miso; 195 196 genvar j; 197 198 generate 199 for (j = 0; j < 16; j = j + 1) 200 begin : CONFIGURATION_OUTPUT 201 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16]; 235 202 end 236 else 237 begin 238 cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data; 203 endgenerate 204 205 configuration configuration_unit ( 206 .clock(sys_clock), 207 .reset(cfg_reset), 208 .bus_ssel(bus_ssel[0]), 209 .bus_wren(bus_wren), 210 .bus_addr(bus_addr[3:0]), 211 .bus_mosi(bus_mosi), 212 .bus_miso(bus_miso[0]), 213 .bus_busy(bus_busy[0]), 214 .cfg_bits(int_cfg_bits)); 215 216 generate 217 for (j = 0; j < 3; j = j + 1) 218 begin : MUX_DATA 219 assign int_mux_data[j] = { 220 {ana_good[j], 11'd0}, 221 ana_data[j], 222 ana_base[j], 223 uwt_a3[j][20:9], 224 uwt_a2[j][17:6], 225 uwt_a1[j][14:3], 226 adc_data[j]}; 239 227 end 240 end 241 242 adc_fifo #(.W(48)) adc_fifo_unit ( 243 .adc_clk(ADC_FCO), 244 .adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}), 245 .clk(sys_clk), 246 .data_ready(data_ready), 247 .data({cmp_data, int_data[2], int_data[1], int_data[0]})); 248 249 genvar i; 228 endgenerate 229 230 assign cfg_mux_selector = {cfg_bits[11], cfg_bits[10]}; 231 232 lpm_mux #( 233 .lpm_size(21), 234 .lpm_type("LPM_MUX"), 235 .lpm_width(12), 236 .lpm_widths(5)) trg_mux_unit ( 237 .sel(cfg_mux_selector[28:24]), 238 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}), 239 .result(trg_mux_data)); 250 240 251 241 generate 252 for (i = 0; i < N; i = i + 1) 253 begin : MCA_CHAIN 254 255 assign cfg_polarity[i] = cfg_memory[10][4*i]; 256 assign cfg_baseline[i] = cfg_memory[11+i][11:0]; 257 assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0]; 258 assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0]; 259 260 assign osc_mux_sel[i] = cfg_memory[20+i][3:0]; 261 assign trg_mux_sel[i] = cfg_memory[20+i][7:4]; 262 263 assign hst_mux_sel[i] = cfg_memory[23+i][3:0]; 264 assign bln_mux_sel[i] = cfg_memory[23+i][7:4]; 265 266 assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]); 267 268 uwt_bior31 #(.L(1)) uwt_1_unit ( 269 .clk(sys_clk), 270 .data_ready(data_ready), 271 .x({20'h00000, data[i]}), 272 .d(uwt_d1[i]), 273 .a(uwt_a1[i]), 274 .peak(uwt_peak1[i]), 275 .flag(uwt_flag1[i])); 276 277 uwt_bior31 #(.L(2)) uwt_2_unit ( 278 .clk(sys_clk), 279 .data_ready(data_ready), 280 .x(uwt_a1[i]), 281 .d(uwt_d2[i]), 282 .a(uwt_a2[i]), 283 .peak(uwt_peak2[i]), 284 .flag(uwt_flag2[i])); 285 286 uwt_bior31 #(.L(3)) uwt_3_unit ( 287 .clk(sys_clk), 288 .data_ready(data_ready), 289 .x(uwt_a2[i]), 290 .d(uwt_d3[i]), 291 .a(uwt_a3[i]), 292 .peak(uwt_peak3[i]), 293 .flag(uwt_flag3[i])); 294 242 for (j = 0; j < 3; j = j + 1) 243 begin : OSC_CHAIN 244 295 245 lpm_mux #( 296 .lpm_size( 7),246 .lpm_size(21), 297 247 .lpm_type("LPM_MUX"), 298 248 .lpm_width(12), 299 .lpm_widths(3)) osc_mux_unit ( 300 .sel(osc_mux_sel[i][2:0]), 301 .data({ {ana_peak_debug[i], 11'd0}, 302 hst_data[i], 303 // uwt_d3[i][11:0], 304 bln_baseline[i], 305 uwt_a3[i][20:9], 306 uwt_a2[i][17:6], 307 uwt_a1[i][14:3], 308 data[i] }), 309 .result(osc_mux_data[i])); 310 311 lpm_mux #( 312 .lpm_size(7), 313 .lpm_type("LPM_MUX"), 314 .lpm_width(12), 315 .lpm_widths(3)) trg_mux_unit ( 316 .sel(trg_mux_sel[i][2:0]), 317 .data({ {ana_peak_ready[i], 11'd0}, 318 hst_data[i], 319 // uwt_d3[i][11:0], 320 bln_baseline[i], 321 uwt_a3[i][20:9], 322 uwt_a2[i][17:6], 323 uwt_a1[i][14:3], 324 data[i] }), 325 .result(trg_mux_data[i])); 326 327 lpm_mux #( 328 .lpm_size(2), 329 .lpm_type("LPM_MUX"), 330 .lpm_width(13), 331 .lpm_widths(1)) hst_mux_unit ( 332 .sel(hst_mux_sel[i][0]), 333 .data({ {uwt_peak3[i][11:0], ana_peak_ready[i]}, 334 {data[i], data_ready} }), 335 .result(hst_mux_data[i])); 336 337 lpm_mux #( 338 .lpm_size(2), 339 .lpm_type("LPM_MUX"), 340 .lpm_width(12), 341 .lpm_widths(1)) bln_mux_unit ( 342 .sel(bln_mux_sel[i][0]), 343 .data({bln_baseline[i], cfg_baseline[i]}), 344 .result(bln_mux_data[i])); 345 346 baseline baseline_unit ( 347 .clk(sys_clk), 348 .reset(bln_reset[i]), 349 .data_ready(data_ready), 350 .uwt_flag(uwt_flag3[i]), 351 .uwt_data(uwt_peak3[i]), 352 .baseline(bln_baseline[i])); 353 354 analyser analyser_unit ( 355 .clk(sys_clk), 356 .reset(ana_reset[i]), 357 .data_ready(data_ready), 358 .uwt_flag(uwt_flag3[i]), 359 .peak_ready(ana_peak_ready[i]), 360 .peak_debug(ana_peak_debug[i])); 361 362 suppression suppression_unit ( 363 .clk(sys_clk), 364 .data(hst_mux_data[i][12:1]), 365 .baseline(bln_mux_data[i]), 366 .result(hst_data[i])); 367 368 assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]); 369 370 histogram #(.W(32)) histogram_unit ( 371 .clk(sys_clk), 372 .reset(hst_reset[i]), 373 .data_ready(hst_data_ready[i]), 374 .data(hst_data[i]), 375 .address(hst_addr[i]), 376 .q(hst_q[i])); 377 378 trigger trigger_unit ( 379 .clk(sys_clk), 380 .reset(trg_reset[i]), 381 .data_ready(data_ready), 382 .data(trg_mux_data[i]), 383 .threshold(cfg_trg_threshold[i]), 384 .trigger(osc_trig[i])); 385 386 387 oscilloscope oscilloscope_unit ( 388 .clk(sys_clk), 389 .reset(osc_reset[i]), 390 .data_ready(data_ready), 391 .data(osc_mux_data[i]), 392 .trigger(osc_trig[i]), 393 .address(osc_addr[i]), 394 .start_address(osc_start_addr[i]), 395 .q(osc_q[i])); 249 .lpm_widths(5)) osc_mux_unit ( 250 .sel(cfg_mux_selector[j*8+4:j*8]), 251 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}), 252 .result(osc_mux_data[j])); 253 396 254 end 397 255 endgenerate 398 256 399 always @* 400 begin 401 for (j = 0; j < N; j = j + 1) 402 begin 403 osc_reset[j] = 1'b0; 404 osc_addr[j] = 10'b0; 405 hst_reset[j] = 1'b0; 406 hst_addr[j] = 12'b0; 257 trigger trigger_unit ( 258 .clock(sys_clock), 259 .frame(sys_frame), 260 .reset(cfg_bits[12][14]), 261 .cfg_data(cfg_bits[12][11:0]), 262 .trg_data(trg_mux_data), 263 .trg_flag(trg_flag)); 264 265 oscilloscope oscilloscope_unit ( 266 .clock(sys_clock), 267 .frame(sys_frame), 268 .reset(cfg_bits[12][13]), 269 .cfg_data({cfg_bits[12][12], cfg_bits[13]}), 270 .trg_flag(trg_flag), 271 .osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}), 272 .ram_wren(RAM_WE), 273 .ram_addr(RAM_ADDR), 274 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}), 275 .bus_ssel(bus_ssel[1]), 276 .bus_wren(bus_wren), 277 .bus_addr(bus_addr[19:0]), 278 .bus_mosi(bus_mosi), 279 .bus_miso(bus_miso[1]), 280 .bus_busy(bus_busy[1])); 281 282 generate 283 for (j = 0; j < 3; j = j + 1) 284 begin : MCA_CHAIN 285 286 assign int_data[j] = (cfg_bits[0][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]); 287 288 uwt_bior31 #(.L(1)) uwt_1_unit ( 289 .clock(sys_clock), 290 .frame(sys_frame), 291 .reset(1'b0), 292 .x({20'h00000, int_data[j]}), 293 .d(uwt_d1[j]), 294 .a(uwt_a1[j]), 295 .peak(uwt_peak1[j]), 296 .flag(uwt_flag1[j])); 297 298 uwt_bior31 #(.L(2)) uwt_2_unit ( 299 .clock(sys_clock), 300 .frame(sys_frame), 301 .reset(1'b0), 302 .x(uwt_a1[j]), 303 .d(uwt_d2[j]), 304 .a(uwt_a2[j]), 305 .peak(uwt_peak2[j]), 306 .flag(uwt_flag2[j])); 307 308 uwt_bior31 #(.L(3)) uwt_3_unit ( 309 .clock(sys_clock), 310 .frame(sys_frame), 311 .reset(1'b0), 312 .x(uwt_a2[j]), 313 .d(uwt_d3[j]), 314 .a(uwt_a3[j]), 315 .peak(uwt_peak3[j]), 316 .flag(uwt_flag3[j])); 317 318 analyser analyser_unit ( 319 .clock(sys_clock), 320 .frame(sys_frame), 321 .reset(cfg_bits[2+2*j][12]), 322 .cfg_data({cfg_bits[2+2*j][11:0], cfg_bits[1+2*j][12:0]}), 323 .uwt_flag(uwt_flag3[j]), 324 .uwt_data(uwt_peak3[j]), 325 .ana_good(ana_good[j]), 326 .ana_data(ana_data[j]), 327 .ana_base(ana_base[j])); 328 329 histogram histogram_unit ( 330 .clock(sys_clock), 331 .frame(sys_frame), 332 .reset(cfg_bits[7+j][13]), 333 .cfg_data(cfg_bits[7+j][12:0]), 334 .hst_good(ana_good[j]), 335 .hst_data(ana_data[j]), 336 .bus_ssel(bus_ssel[2+j]), 337 .bus_wren(bus_wren), 338 .bus_addr(bus_addr[12:0]), 339 .bus_mosi(bus_mosi), 340 .bus_miso(bus_miso[2+j]), 341 .bus_busy(bus_busy[2+j])); 342 407 343 end 408 409 case(mux_type) 410 1'b0: 411 begin 412 osc_reset[mux_chan] = mux_reset; 413 osc_addr[mux_chan] = mux_addr[9:0]; 414 mux_max_byte = 2'd1; 415 mux_min_addr = {6'd0, osc_start_addr[mux_chan]}; 416 mux_max_addr = 16'd1023; 417 end 418 419 1'b1: 420 begin 421 hst_reset[mux_chan] = mux_reset; 422 hst_addr[mux_chan] = mux_addr[11:0]; 423 mux_max_byte = 2'd3; 424 mux_min_addr = 16'd0; 425 mux_max_addr = 16'd4095; 426 end 427 endcase 428 end 429 430 always @* 431 begin 432 case ({mux_type, mux_byte}) 433 3'b000: mux_q = osc_q[mux_chan][7:0]; 434 3'b001: mux_q = osc_q[mux_chan][15:8]; 435 436 3'b100: mux_q = hst_q[mux_chan][7:0]; 437 3'b101: mux_q = hst_q[mux_chan][15:8]; 438 3'b110: mux_q = hst_q[mux_chan][23:16]; 439 3'b111: mux_q = hst_q[mux_chan][31:24]; 440 441 default: mux_q = 8'd0; 442 endcase 443 end 444 445 wire i2c_aclr; 446 wire i2c_wrreq; 447 wire i2c_full; 448 wire [15:0] i2c_data; 344 endgenerate 449 345 450 346 i2c_fifo i2c_unit( 451 .clk(sys_clk), 452 .aclr(i2c_aclr), 453 .wrreq(i2c_wrreq), 454 .data(i2c_data), 455 .full(i2c_full), 347 .clock(sys_clock), 348 .reset(i2c_reset), 456 349 /* 457 350 normal connection … … 462 355 */ 463 356 .i2c_sda(I2C_SCL), 464 .i2c_scl(I2C_SDA)); 357 .i2c_scl(I2C_SDA), 358 359 .bus_ssel(bus_ssel[5]), 360 .bus_wren(bus_wren), 361 .bus_mosi(bus_mosi), 362 .bus_busy(bus_busy[5])); 363 364 generate 365 for (j = 0; j < 5; j = j + 1) 366 begin : BUS_OUTPUT 367 assign int_bus_miso[j*16+15:j*16] = bus_miso[j]; 368 end 369 endgenerate 370 371 lpm_mux #( 372 .lpm_size(5), 373 .lpm_type("LPM_MUX"), 374 .lpm_width(16), 375 .lpm_widths(3)) bus_miso_mux_unit ( 376 .sel(bus_addr[30:28]), 377 .data(int_bus_miso), 378 .result(mrg_bus_miso)); 379 380 lpm_mux #( 381 .lpm_size(6), 382 .lpm_type("LPM_MUX"), 383 .lpm_width(1), 384 .lpm_widths(3)) bus_busy_mux_unit ( 385 .sel(bus_addr[30:28]), 386 .data(bus_busy), 387 .result(mrg_bus_busy)); 388 389 /* 390 lpm_or #( 391 .lpm_size(6), 392 .lpm_type("LPM_OR"), 393 .lpm_width(16)) bus_miso_or_unit ( 394 .data(int_bus_miso), 395 .result(mrg_bus_miso)); 396 */ 397 398 lpm_decode #( 399 .lpm_decodes(8), 400 .lpm_type("LPM_DECODE"), 401 .lpm_width(3)) lpm_decode_unit ( 402 .data(bus_addr[30:28]), 403 .eq(bus_ssel), 404 .aclr(), 405 .clken(), 406 .clock(), 407 .enable()); 465 408 466 409 control control_unit ( 467 .clk(sys_clk), 468 .cfg_reset(cfg_reset), 469 .cfg_src_data(cfg_memory[cfg_src_addr[4:0]]), 470 .cfg_src_addr(cfg_src_addr), 471 .cfg_dst_data(cfg_dst_data), 472 .cfg_dst_addr(cfg_dst_addr), 410 .clock(sys_clock), 473 411 .rx_empty(usb_rx_empty), 474 412 .tx_full(usb_tx_full), 475 413 .rx_data(usb_rx_data), 476 .mux_max_byte(mux_max_byte),477 .mux_min_addr(mux_min_addr),478 .mux_max_addr(mux_max_addr),479 .mux_q(mux_q),480 .mux_reset(mux_reset),481 .mux_type(mux_type),482 .mux_chan(mux_chan),483 .mux_byte(mux_byte),484 .mux_addr(mux_addr),485 414 .rx_rdreq(usb_rx_rdreq), 486 415 .tx_wrreq(usb_tx_wrreq), 487 416 .tx_data(usb_tx_data), 488 .ram_we(RAM_WE), 489 .ram_addr(RAM_ADDR), 490 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}), 491 .ept_data_ready(data_ready), 492 .ept_data({cmp_data, data[2], data[1], data[0]}), 493 .i2c_wrreq(i2c_wrreq), 494 .i2c_data(i2c_data), 495 .i2c_full(i2c_full), 417 .bus_wren(bus_wren), 418 .bus_addr(bus_addr), 419 .bus_mosi(bus_mosi), 420 .bus_miso(mrg_bus_miso), 421 .bus_busy(mrg_bus_busy), 496 422 .led(LED)); 497 423 -
trunk/MultiChannelUSB/adc_fifo.v
r86 r90 7 7 input wire [W-1:0] adc_data, 8 8 9 input wire clk,10 output wire data_ready,11 output wire [W-1:0] data9 input wire sys_clk, 10 output wire sys_good, 11 output wire [W-1:0] sys_data 12 12 ); 13 13 … … 15 15 reg [W-1:0] int_data; 16 16 17 reg state, int_rdreq, int_ data_ready;17 reg state, int_rdreq, int_good; 18 18 wire int_wrfull, int_rdempty; 19 19 … … 33 33 .aclr(1'b0), 34 34 .data(adc_data), 35 .rdclk( clk),35 .rdclk(sys_clk), 36 36 .rdreq((~int_rdempty) & int_rdreq), 37 37 .wrclk(adc_clk), … … 45 45 .wrusedw()); 46 46 47 always @(posedge clk)47 always @(posedge sys_clk) 48 48 begin 49 49 case (state) … … 51 51 begin 52 52 int_rdreq <= 1'b1; 53 int_ data_ready<= 1'b0;53 int_good <= 1'b0; 54 54 state <= 1'b1; 55 55 end … … 61 61 int_data <= int_q; 62 62 int_rdreq <= 1'b0; 63 int_ data_ready<= 1'b1;63 int_good <= 1'b1; 64 64 state <= 1'b0; 65 65 end … … 68 68 end 69 69 70 assign data_ready = int_data_ready;71 assign data = int_data;70 assign sys_good = int_good; 71 assign sys_data = int_data; 72 72 73 73 endmodule -
trunk/MultiChannelUSB/analyser.v
r89 r90 1 1 module analyser 2 2 ( 3 input wire cl k, reset,4 input wire data_ready,3 input wire clock, frame, reset, 4 input wire [12:0] cfg_data, 5 5 input wire [1:0] uwt_flag, 6 output wire peak_ready 6 input wire [11:0] uwt_data, 7 output wire ana_good, 8 output wire [11:0] ana_data, 9 output wire [11:0] ana_base 7 10 ); 8 11 9 reg flag_reg, flag_next; 10 reg [1:0] state_reg, state_next; 12 reg state_reg, state_next; 11 13 reg [4:0] counter_reg, counter_next; 12 reg peak_ready_reg; 14 reg good_reg, good_next; 15 reg [11:0] data_reg, data_next; 13 16 17 reg [19:0] buffer_reg [31:0]; 18 reg [19:0] buffer_next [31:0]; 19 20 wire [19:0] sample = {8'd0, uwt_data}; 21 wire [11:0] baseline = buffer_reg[31][16:5]; 14 22 wire counter_max = (&counter_reg); 15 wire peak_ready_int = (flag_reg & data_ready & uwt_flag[0] & counter_max);16 23 17 always @(posedge clk) 24 integer i; 25 26 always @(posedge clock) 18 27 begin 19 28 if (reset) 20 29 begin 21 flag_reg <= 1'b0; 22 state_reg <= 2'd0; 30 state_reg <= 1'b0; 23 31 counter_reg <= 5'd0; 32 good_reg <= 1'b0; 33 data_reg <= 12'd0; 34 for(i = 0; i <= 31; i = i + 1) 35 begin 36 buffer_reg[i] <= 20'hfffff; 37 end 24 38 end 25 39 else 26 40 begin 27 flag_reg <= flag_next;28 41 state_reg <= state_next; 29 42 counter_reg <= counter_next; 43 good_reg <= good_next; 44 data_reg <= data_next; 45 46 for(i = 0; i <= 31; i = i + 1) 47 begin 48 buffer_reg[i] <= buffer_next[i]; 49 end 30 50 end 31 51 end … … 33 53 always @* 34 54 begin 35 flag_next = flag_reg;36 55 state_next = state_reg; 37 56 counter_next = counter_reg; 57 good_next = good_reg; 58 data_next = data_reg; 59 60 for(i = 0; i <= 31; i = i + 1) 61 begin 62 buffer_next[i] = buffer_reg[i]; 63 end 64 38 65 case (state_reg) 39 0: // skip first 16samples66 0: // skip first 32 samples 40 67 begin 41 flag_next = 1'b0; 42 if (data_ready) 68 if (frame) 43 69 begin 44 70 counter_next = counter_reg + 5'd1; 45 71 if (counter_max) 46 72 begin 47 state_next = 2'd1;73 state_next = 1'b1; 48 74 end 49 75 end 50 76 end 51 77 52 1: // skip first 16 minima78 1: 53 79 begin 54 flag_next = 1'b0; 55 if (data_ready & uwt_flag[1]) 80 if (frame) 56 81 begin 57 counter_next = counter_reg + 5'd1; 82 83 if (cfg_data[12]) 84 begin 85 if (uwt_data > baseline) 86 begin 87 data_next = uwt_data - baseline; 88 end 89 else 90 begin 91 data_next = 12'd0; 92 end 93 end 94 else 95 begin 96 if (uwt_data > cfg_data[11:0]) 97 begin 98 data_next = uwt_data - cfg_data[11:0]; 99 end 100 else 101 begin 102 data_next = 12'd0; 103 end 104 end 105 106 107 for(i = 0; i < 31; i = i + 1) 108 begin 109 buffer_next[i+1] = buffer_reg[i] + sample; 110 end 111 buffer_next[0] = sample; 112 113 good_next = uwt_flag[0] & counter_max; 114 115 // skip first 32 baseline samples 116 // skip 32 samples after peak 58 117 if (counter_max) 59 118 begin 60 state_next = 2'd2; 119 if (uwt_flag[0]) 120 begin 121 counter_next = 5'd0; 122 end 61 123 end 62 end 63 end 64 65 2: 66 begin 67 flag_next = 1'b1; 68 if (data_ready) 69 begin 70 if (~counter_max) 124 else 71 125 begin 72 126 counter_next = counter_reg + 5'd1; 73 127 end 74 if (peak_ready_int) 75 begin 76 counter_next = 5'd0; 77 end 78 end 79 end 80 81 default: 82 begin 83 flag_next = 1'b0; 84 state_next = 2'd0; 85 counter_next = 5'd0; 128 end 86 129 end 87 130 endcase 88 131 end 89 132 90 assign peak_ready = peak_ready_int; 133 assign ana_good = good_reg; 134 assign ana_data = data_reg; 135 assign ana_base = baseline; 91 136 92 137 endmodule -
trunk/MultiChannelUSB/control.v
r87 r90 1 1 module control 2 2 ( 3 input wire clk, 4 5 output wire cfg_reset, 6 input wire [15:0] cfg_src_data, 7 output wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr, 3 input wire clock, reset, 8 4 9 5 input wire rx_empty, tx_full, 10 6 input wire [7:0] rx_data, 11 7 12 input wire [1:0] mux_max_byte, 13 input wire [15:0] mux_min_addr, mux_max_addr, 14 input wire [7:0] mux_q, 15 16 output wire mux_reset, 17 output wire mux_type, 18 output wire [1:0] mux_chan, 19 output wire [1:0] mux_byte, 20 output wire [15:0] mux_addr, 21 22 output wire rx_rdreq, 23 output wire tx_wrreq, 8 output wire rx_rdreq, tx_wrreq, 24 9 output wire [7:0] tx_data, 25 10 26 output wire ram_we, 27 output wire [19:0] ram_addr, 28 inout wire [17:0] ram_data, 29 30 input wire ept_data_ready, 31 input wire [47:0] ept_data, 32 33 output wire i2c_wrreq, 34 output wire [15:0] i2c_data, 35 input wire i2c_full, 11 output wire bus_wren, 12 output wire [31:0] bus_addr, 13 output wire [15:0] bus_mosi, 14 15 input wire [15:0] bus_miso, 16 input wire bus_busy, 36 17 37 18 output wire led … … 39 20 40 21 reg [23:0] led_counter; 41 reg [19:0] ram_counter; 42 reg [10:0] tst_counter; 43 reg [15:0] int_addr, int_max_addr; 22 23 reg int_bus_wren; 24 reg [31:0] int_bus_addr; 25 reg [31:0] int_bus_cntr; 26 reg [15:0] int_bus_mosi; 44 27 45 28 reg int_rdreq, int_wrreq; 46 reg int_type, int_reset;47 reg [1:0] int_chan, int_byte, int_max_byte;48 29 reg [7:0] int_data; 49 30 reg int_led; 50 31 51 reg [15:0] int_i2c_data;52 reg int_i2c_wrreq;53 54 reg [47:0] int_ept_data;55 56 reg int_cfg_reset;57 reg [15:0] int_dst_data, int_dst_addr;58 59 wire crc_error = 1'b0;60 reg crc_reset;61 32 reg [1:0] byte_counter; 62 33 reg [4:0] idle_counter; 63 34 64 35 reg [4:0] state; 65 66 wire [15:0] src, dst; 36 37 reg [31:0] address, counter; 38 39 reg [15:0] prefix; 40 41 wire [15:0] dest, data; 67 42 68 43 reg [7:0] buffer [3:0]; 69 44 70 assign src = (buffer[0][7]) ? cfg_src_data : {buffer[2], buffer[3]}; 71 assign dst = {1'b0, buffer[0][6:0], buffer[1]}; 72 73 reg int_ram_we; 74 reg [17:0] int_ram_data; 75 wire [17:0] int_ram_q; 76 wire [17:0] opt_ram_we; 77 assign ram_we = ~int_ram_we; 78 assign int_ram_q = ram_data; 79 // assign ram_data = int_ram_we ? int_ram_data : 18'bz; 80 // assign ram_addr = {ram_counter[18:5],1'd0,ram_counter[4:0]}; 81 assign ram_addr = ram_counter; 82 83 genvar j; 84 generate 85 for (j = 0; j < 18; j = j + 1) 86 begin : SRAM_WE 87 assign opt_ram_we[j] = int_ram_we; 88 assign ram_data[j] = opt_ram_we[j] ? int_ram_data[j] : 1'bz; 89 end 90 endgenerate 91 92 always @(posedge clk) 45 assign dest = {buffer[0], buffer[1]}; 46 assign data = {buffer[2], buffer[3]}; 47 48 always @(posedge clock) 93 49 begin 94 50 if (~rx_empty) … … 114 70 int_rdreq <= 1'b1; 115 71 int_wrreq <= 1'b0; 116 int_type <= 1'b0;117 int_chan <= 2'd0;118 int_byte <= 2'd0;119 int_reset <= 1'b0;120 crc_reset <= 1'b0;121 int_ram_we <= 1'b0;122 int_ram_data <= 16'd0;123 ram_counter <= 20'd0;124 72 idle_counter <= 5'd0; 125 73 byte_counter <= 2'd0; 126 int_cfg_reset <= 1'b0;127 74 state <= 5'd1; 128 75 end … … 130 77 1: 131 78 begin 132 // read 8bytes79 // read 4 bytes 133 80 if (~rx_empty) 134 81 begin … … 148 95 begin 149 96 int_rdreq <= 1'b0; 150 crc_reset <= 1'b1;151 97 state <= 5'd0; 152 98 end … … 156 102 2: 157 103 begin 158 crc_reset <= 1'b1; 159 if (~crc_error) 160 begin 161 int_dst_addr <= dst; 162 int_dst_data <= src; 163 // memory[dst[3:0]] <= src; 164 165 case (dst) 166 16'h0000: 167 begin 168 int_cfg_reset <= 1'b1; 169 state <= 5'd0; 170 end 171 172 16'h0001: 173 begin 174 int_type <= src[4]; 175 int_chan <= src[1:0]; 176 int_reset <= 1'b1; 177 state <= 5'd0; 178 end 179 180 16'h0002: 181 begin 182 int_type <= src[4]; 183 int_chan <= src[1:0]; 184 state <= 5'd3; 185 end 186 187 16'h0003: 188 begin 189 tst_counter <= 11'd0; 190 state <= 5'd7; 191 end 192 16'h0004: 193 begin 194 int_ram_we <= 1'b1; 195 int_ram_data <= 18'd0; 196 ram_counter <= 20'd0; 197 state <= 5'd10; 198 end 199 16'h0005: 200 begin 201 int_i2c_data <= src; 202 int_i2c_wrreq <= 1'b1; 203 state <= 5'd16; 204 end 205 16'h0006: 206 begin 207 int_ram_we <= 1'b1; 208 int_ram_data <= 18'd0; 209 ram_counter <= 20'd0; 210 state <= 5'd17; 211 end 212 213 default: 214 begin 215 state <= 5'd0; 216 end 217 endcase 218 end 219 end 220 221 // mux transfer 104 case (dest) 105 16'h0000: 106 begin 107 // reset 108 prefix <= 16'd0; 109 state <= 5'd0; 110 end 111 112 113 16'h0001: 114 begin 115 // prefix register 116 prefix <= data; 117 state <= 5'd0; 118 end 119 120 121 16'h0002: 122 begin 123 // address register 124 address <= {prefix, data}; 125 prefix <= 16'd0; 126 state <= 5'd0; 127 end 128 129 16'h0003: 130 begin 131 // counter register 132 counter <= {prefix, data}; 133 prefix <= 16'd0; 134 state <= 5'd0; 135 end 136 137 16'h0004: 138 begin 139 // single write 140 int_bus_addr <= address; 141 int_bus_mosi <= data; 142 int_bus_wren <= 1'b1; 143 prefix <= 16'd0; 144 state <= 5'd3; 145 end 146 147 16'h0005: 148 begin 149 // multi read 150 int_bus_addr <= address; 151 int_bus_cntr <= counter; 152 int_bus_wren <= 1'b0; 153 prefix <= 16'd0; 154 state <= 5'd4; 155 end 156 157 default: 158 begin 159 prefix <= 16'd0; 160 state <= 5'd0; 161 end 162 endcase 163 end 164 165 // single write 222 166 3: 223 167 begin 224 crc_reset <= 1'b0; 225 int_addr <= mux_min_addr; 226 int_max_addr <= mux_min_addr + mux_max_addr; 227 int_max_byte <= mux_max_byte; 228 int_byte <= 2'd0; 229 state <= 5'd4; 230 end 231 168 if (~bus_busy) 169 begin 170 int_bus_addr <= 32'd0; 171 int_bus_mosi <= 16'd0; 172 int_bus_wren <= 1'b0; 173 state <= 5'd0; 174 end 175 end 176 177 // multi read 232 178 4: 233 179 begin 234 int_wrreq <= 1'b0; 235 state <= 5'd5; 180 if (bus_busy) 181 begin 182 buffer[0] <= 8'd1; 183 buffer[1] <= 8'd0; 184 int_bus_cntr <= 32'd0; 185 state <= 5'd7; 186 end 187 else 188 begin 189 buffer[0] <= 8'd2; 190 buffer[1] <= 8'd0; 191 state <= 5'd6; 192 end 236 193 end 237 194 238 195 5: 239 196 begin 197 buffer[0] <= bus_miso[7:0]; 198 buffer[1] <= bus_miso[15:8]; 240 199 state <= 5'd6; 241 200 end … … 243 202 6: 244 203 begin 204 int_bus_addr <= int_bus_addr + 32'd1; 205 state <= 5'd7; 206 end 207 208 7: 209 begin 245 210 if (~tx_full) 246 211 begin 247 int_data <= mux_q;212 int_data <= buffer[0]; 248 213 int_wrreq <= 1'b1; 249 if ((int_byte == int_max_byte) && (int_addr == int_max_addr)) 250 begin 251 state <= 5'd0; 214 state <= 5'd8; 215 end 216 end 217 218 8: 219 begin 220 int_data <= buffer[1]; 221 state <= 5'd9; 222 end 223 224 9: 225 begin 226 if (~tx_full) 227 begin 228 int_wrreq <= 1'b0; 229 if (|int_bus_cntr) 230 begin 231 state <= 5'd5; 232 int_bus_cntr <= int_bus_cntr - 32'd1; 252 233 end 253 234 else 254 235 begin 255 state <= 5'd4; 256 if (int_byte == int_max_byte) 257 begin 258 int_addr <= int_addr + 16'd1; 259 int_byte <= 2'd0; 260 end 261 else 262 begin 263 int_byte <= int_byte + 2'd1; 264 end 265 end 266 end 267 end 268 269 // tst transfer 270 7: 271 begin 272 crc_reset <= 1'b0; 273 int_data <= tst_counter; 274 int_wrreq <= 1'b1; 275 tst_counter <= tst_counter + 11'd1; 276 state <= 5'd8; 277 end 278 8: 279 begin 280 if (~tx_full) 281 begin 282 int_data <= tst_counter; 283 if (&tst_counter) 284 begin 285 state <= 5'd9; 286 end 287 else 288 begin 289 tst_counter <= tst_counter + 11'd1; 290 end 291 end 292 end 293 9: 294 begin 295 if (~tx_full) 296 begin 297 int_wrreq <= 1'b0; 298 state <= 5'd0; 299 end 300 end 301 // ram transfer 302 10: 303 begin 304 crc_reset <= 1'b0; 305 state <= 5'd11; 306 end 307 11: 308 begin 309 int_ram_data[8:1] <= ram_counter[7:0]; 310 // int_ram_data[8:1] <= 8'd0; 311 if (&ram_counter[18:0]) 312 begin 313 state <= 5'd12; 314 end 315 else 316 begin 317 state <= 5'd10; 318 ram_counter <= ram_counter + 20'd1; 319 end 320 end 321 12: 322 begin 323 int_ram_we <= 1'b0; 324 int_ram_data <= 18'd0; 325 ram_counter <= 20'd0; 326 state <= 5'd13; 327 end 328 13: 329 begin 330 int_wrreq <= 1'b0; 331 state <= 5'd14; 332 end 333 14: 334 begin 335 state <= 5'd15; 336 end 337 15: 338 begin 339 if (~tx_full) 340 begin 341 int_data <= int_ram_q[8:1]; 342 int_wrreq <= 1'b1; 343 if (&ram_counter[18:0]) 344 begin 345 state <= 5'd0; 346 end 347 else 348 begin 349 state <= 5'd13; 350 ram_counter <= ram_counter + 20'd1; 351 end 352 end 353 end 354 355 // i2c write 356 16: 357 begin 358 crc_reset <= 1'b0; 359 if (~i2c_full) 360 begin 361 int_i2c_wrreq <= 1'b0; 362 state <= 5'd0; 363 end 364 end 365 366 // long sample transfer 367 17: 368 begin 369 crc_reset <= 1'b0; 370 if (ept_data_ready) 371 begin 372 ram_counter <= ram_counter + 20'd1; 373 int_ept_data <= ept_data; 374 state <= 5'd18; 375 end 376 end 377 18: 378 begin 379 int_ram_data[8:1] <= int_ept_data[7:0]; 380 int_ram_data[17:10] <= int_ept_data[15:8]; 381 ram_counter <= ram_counter + 20'd1; 382 state <= 5'd19; 383 end 384 19: 385 begin 386 int_ram_data[8:1] <= int_ept_data[23:16]; 387 int_ram_data[17:10] <= int_ept_data[31:24]; 388 ram_counter <= ram_counter + 20'd1; 389 state <= 5'd20; 390 end 391 392 20: 393 begin 394 int_ram_data[8:1] <= int_ept_data[39:32]; 395 int_ram_data[17:10] <= int_ept_data[47:40]; 396 if (&ram_counter) 397 begin 398 int_ram_we <= 1'b0; 399 ram_counter <= 19'd0; 400 state <= 5'd21; 401 end 402 else 403 begin 404 state <= 5'd17; 405 end 406 end 407 408 21: 409 begin 410 int_wrreq <= 1'b0; 411 state <= 5'd22; 412 end 413 414 22: 415 begin 416 state <= 5'd23; 417 end 418 419 23: 420 begin 421 if (~tx_full) 422 begin 423 int_data <= int_ram_q[8:1]; 424 int_wrreq <= 1'b1; 425 state <= 5'd24; 426 end 427 end 428 429 24: 430 begin 431 int_data <= int_ram_q[17:10]; 432 state <= 5'd25; 433 end 434 435 25: 436 begin 437 if (~tx_full) 438 begin 439 int_wrreq <= 1'b0; 440 if (&ram_counter) 441 begin 442 state <= 5'd0; 443 end 444 else 445 begin 446 state <= 5'd21; 447 ram_counter <= ram_counter + 20'd1; 236 state <= 5'd0; 448 237 end 449 238 end … … 456 245 endcase 457 246 end 458 459 assign cfg_reset = int_cfg_reset; 460 assign cfg_src_addr = {buffer[2], buffer[3]}; 461 assign cfg_dst_data = int_dst_data; 462 assign cfg_dst_addr = int_dst_addr; 463 assign mux_reset = int_reset; 464 assign mux_type = int_type; 465 assign mux_chan = int_chan; 466 assign mux_byte = int_byte; 467 assign mux_addr = int_addr; 247 248 assign bus_wren = int_bus_wren; 249 assign bus_addr = int_bus_addr; 250 assign bus_mosi = int_bus_mosi; 468 251 assign rx_rdreq = int_rdreq & (~rx_empty); 469 252 assign tx_wrreq = int_wrreq & (~tx_full); 470 253 assign tx_data = int_data; 471 assign i2c_wrreq = int_i2c_wrreq;472 assign i2c_data = int_i2c_data;473 254 assign led = int_led; 474 255 -
trunk/MultiChannelUSB/histogram.v
r88 r90 1 1 module histogram 2 #(3 parameter W = 32 // bin resolution4 )5 2 ( 6 input wire clk, reset, 7 input wire data_ready, 8 input wire [11:0] data, address, 9 output wire [W-1:0] q 3 input wire clock, frame, reset, 4 5 input wire [40:0] cfg_data, 6 7 input wire hst_good, 8 input wire [11:0] hst_data, 9 10 input wire bus_ssel, bus_wren, 11 input wire [12:0] bus_addr, 12 input wire [15:0] bus_mosi, 13 14 output wire [15:0] bus_miso, 15 output wire bus_busy 10 16 ); 11 17 12 18 // signal declaration 13 reg [3:0] state_reg, state_next; 14 reg wren_reg, wren_next; 15 reg [11:0] addr_reg, addr_next; 16 reg [W-1:0] data_reg, data_next; 17 18 wire [W-1:0] q_a_wire, q_b_wire; 19 reg [3:0] int_case_reg, int_case_next; 20 reg int_wren_reg, int_wren_next; 21 reg [11:0] int_addr_reg, int_addr_next; 22 reg [31:0] int_data_reg, int_data_next; 23 24 reg [12:0] bus_addr_reg, bus_addr_next; 25 reg [15:0] bus_miso_reg, bus_miso_next; 26 27 reg bus_wren_reg, bus_wren_next; 28 reg [15:0] bus_mosi_reg, bus_mosi_next; 29 30 wire [31:0] q_a_wire; 31 wire [15:0] q_b_wire; 19 32 20 33 altsyncram #( … … 28 41 .lpm_type("altsyncram"), 29 42 .numwords_a(4096), 30 .numwords_b( 4096),43 .numwords_b(8192), 31 44 .operation_mode("BIDIR_DUAL_PORT"), 32 45 .outdata_aclr_a("NONE"), … … 36 49 .power_up_uninitialized("FALSE"), 37 50 .read_during_write_mode_mixed_ports("OLD_DATA"), 51 .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"), 52 .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"), 38 53 .widthad_a(12), 39 .widthad_b(1 2),40 .width_a( W),41 .width_b( W),54 .widthad_b(13), 55 .width_a(32), 56 .width_b(16), 42 57 .width_byteena_a(1), 43 58 .width_byteena_b(1), 44 59 .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit( 45 .wren_a( wren_reg),46 .clock0(cl k),47 .wren_b( 1'b0),48 .address_a( addr_reg),49 .address_b( address),50 .data_a( data_reg),51 .data_b( ),60 .wren_a(int_wren_reg), 61 .clock0(clock), 62 .wren_b(bus_wren_reg), 63 .address_a(int_addr_reg), 64 .address_b(bus_addr_reg), 65 .data_a(int_data_reg), 66 .data_b(bus_mosi_reg), 52 67 .q_a(q_a_wire), 53 68 .q_b(q_b_wire), … … 68 83 69 84 // body 70 always @(posedge cl k)85 always @(posedge clock) 71 86 begin 72 87 if (reset) 73 88 begin 74 wren_reg <= 1'b1; 75 addr_reg <= 12'd0; 76 data_reg <= 32'd0; 77 state_reg <= 4'b1; 89 int_wren_reg <= 1'b1; 90 int_addr_reg <= 12'd0; 91 int_data_reg <= 32'd0; 92 int_case_reg <= 4'b1; 93 bus_addr_reg <= 13'd0; 94 bus_miso_reg <= 16'd0; 95 bus_wren_reg <= 1'b0; 96 bus_mosi_reg <= 16'd0; 78 97 end 79 98 else 80 99 begin 81 wren_reg <= wren_next; 82 addr_reg <= addr_next; 83 data_reg <= data_next; 84 state_reg <= state_next; 100 int_wren_reg <= int_wren_next; 101 int_addr_reg <= int_addr_next; 102 int_data_reg <= int_data_next; 103 int_case_reg <= int_case_next; 104 bus_addr_reg <= bus_addr_next; 105 bus_miso_reg <= bus_miso_next; 106 bus_wren_reg <= bus_wren_next; 107 bus_mosi_reg <= bus_mosi_next; 108 end 109 end 110 111 always @* 112 begin 113 bus_addr_next = bus_addr_reg; 114 bus_miso_next = bus_miso_reg; 115 116 bus_wren_next = 1'b0; 117 bus_mosi_next = bus_mosi_reg; 118 119 if (bus_ssel) 120 begin 121 bus_miso_next = q_b_wire; 122 bus_addr_next = bus_addr; 123 bus_wren_next = bus_wren; 124 if (bus_wren) 125 begin 126 bus_mosi_next = bus_mosi; 127 end 85 128 end 86 129 end … … 88 131 always @* 89 132 begin 90 wren_next = wren_reg; 91 addr_next = addr_reg; 92 data_next = data_reg; 93 state_next = state_reg; 94 case (state_reg) 133 int_wren_next = int_wren_reg; 134 int_addr_next = int_addr_reg; 135 int_data_next = int_data_reg; 136 int_case_next = int_case_reg; 137 138 case (int_case_reg) 95 139 0: 96 140 begin 97 // nothing to do 98 wren_next = 1'b0; 99 addr_next = 12'd0; 100 data_next = 32'd0; 101 state_next = 4'd0; 141 int_wren_next = 1'b0; 142 int_addr_next = 12'd0; 143 int_data_next = 32'd0; 102 144 end 103 145 … … 105 147 begin 106 148 // write zeros 107 if (& addr_reg)108 begin 109 wren_next = 1'b0;110 state_next = 4'd2;149 if (&int_addr_reg) 150 begin 151 int_wren_next = 1'b0; 152 int_case_next = 4'd2; 111 153 end 112 154 else 113 155 begin 114 addr_next =addr_reg + 12'd1;156 int_addr_next = int_addr_reg + 12'd1; 115 157 end 116 158 end … … 118 160 2: 119 161 begin 120 wren_next = 1'b0; 121 if (data_ready) 122 begin 123 addr_next = data; 124 state_next = 4'd3; 162 int_wren_next = 1'b0; 163 if (&int_data_reg) 164 begin 165 int_case_next = 4'd0; 166 end 167 else if (frame & hst_good) 168 begin 169 int_addr_next = hst_data; 170 int_case_next = 4'd3; 125 171 end 126 172 end … … 128 174 3: 129 175 begin 130 state_next = 4'd4;176 int_case_next = 4'd4; 131 177 end 132 178 133 179 4: 134 180 begin 135 state_next = 5'd4;181 int_case_next = 4'd5; 136 182 end 137 183 138 184 5: 139 185 begin 140 if (&q_a_wire) 141 begin 142 state_next = 4'd0; 143 end 144 else 145 begin 146 wren_next = 1'b1; 147 data_next = q_a_wire + 32'd1; 148 state_next = 4'd2; 149 end 186 int_wren_next = 1'b1; 187 int_data_next = q_a_wire + 32'd1; 188 int_case_next = 4'd2; 150 189 end 151 190 152 191 default: 153 192 begin 154 wren_next = 1'b0;155 addr_next = 12'd0;156 data_next = 32'd0;157 state_next = 4'd0;193 int_wren_next = 1'b0; 194 int_addr_next = 12'd0; 195 int_data_next = 32'd0; 196 int_case_next = 4'd0; 158 197 end 159 198 endcase … … 161 200 162 201 // output logic 163 assign q = q_b_wire; 202 assign bus_miso = bus_miso_reg; 203 assign bus_busy = 1'b0; 164 204 endmodule -
trunk/MultiChannelUSB/i2c_fifo.v
r84 r90 1 1 module i2c_fifo 2 2 ( 3 input wire clk, aclr, 4 input wire wrreq, 5 input wire [15:0] data, 6 output wire full, 3 input wire clock, reset, 4 5 input wire bus_ssel, bus_wren, 6 input wire [15:0] bus_mosi, 7 8 output wire bus_busy, 7 9 8 10 inout wire i2c_sda, … … 10 12 ); 11 13 12 wire int_rdempty, i 2c_clk, start, stop;14 wire int_rdempty, int_wrfull, i2c_clk, start, stop; 13 15 wire [15:0] int_q; 14 16 15 reg int_rdreq, int_clken, int_sdo, int_scl, int_ack; 17 reg int_bus_busy; 18 reg int_rdreq, int_wrreq, int_clken, int_sdo, int_scl, int_ack; 19 reg [15:0] int_bus_mosi; 16 20 reg [15:0] int_data; 17 21 reg [9:0] counter; … … 34 38 .overflow_checking("ON"), 35 39 .underflow_checking("ON"), 36 .use_eab("O N")) fifo_tx (40 .use_eab("OFF")) fifo_tx ( 37 41 .rdreq((~int_rdempty) & (int_rdreq) & (&counter)), 38 .aclr( aclr),39 .clock(cl k),40 .wrreq( wrreq),41 .data( data),42 .aclr(1'b0), 43 .clock(clock), 44 .wrreq(int_wrreq), 45 .data(int_bus_mosi), 42 46 .empty(int_rdempty), 43 47 .q(int_q), 44 .full( full),48 .full(int_wrfull), 45 49 .almost_empty(), 46 50 .almost_full(), … … 48 52 .usedw()); 49 53 50 always @ (posedge clk) 54 always @ (posedge clock) 55 begin 56 int_bus_busy <= int_wrfull; 57 58 if (bus_ssel) 59 begin 60 if (~int_wrfull & bus_wren) 61 begin 62 int_bus_mosi <= bus_mosi; 63 int_wrreq <= 1'b1; 64 end 65 end 66 67 if (~int_wrfull & int_wrreq) 68 begin 69 int_wrreq <= 1'b0; 70 end 71 72 end 73 74 always @ (posedge clock) 51 75 begin 52 76 counter <= counter + 10'd1; … … 190 214 end 191 215 216 // output logic 217 assign bus_busy = int_bus_busy; 218 192 219 endmodule -
trunk/MultiChannelUSB/oscilloscope.v
r84 r90 1 1 module oscilloscope 2 2 ( 3 input wire clk, reset, 4 input wire data_ready, trigger, 5 input wire [15:0] data, 6 input wire [9:0] address, 7 output wire [9:0] start_address, 8 output wire [15:0] q 3 input wire clock, frame, reset, 4 5 input wire [16:0] cfg_data, 6 7 input wire trg_flag, 8 9 input wire [47:0] osc_data, 10 11 output wire ram_wren, 12 output wire [19:0] ram_addr, 13 inout wire [17:0] ram_data, 14 15 input wire bus_ssel, bus_wren, 16 input wire [19:0] bus_addr, 17 input wire [15:0] bus_mosi, 18 19 output wire [15:0] bus_miso, 20 output wire bus_busy 9 21 ); 10 11 // signal declaration 12 reg [3:0] state_reg, state_next; 13 reg wren_reg, wren_next; 14 reg [9:0] addr_reg, addr_next; 15 reg [15:0] data_reg, data_next; 16 17 reg trig_reg, trig_next; 18 reg [9:0] trig_addr_reg, trig_addr_next; 19 reg [9:0] counter_reg, counter_next; 20 21 wire [15:0] q_wire; 22 23 altsyncram #( 24 .address_reg_b("CLOCK0"), 25 .clock_enable_input_a("BYPASS"), 26 .clock_enable_input_b("BYPASS"), 27 .clock_enable_output_a("BYPASS"), 28 .clock_enable_output_b("BYPASS"), 29 .intended_device_family("Cyclone III"), 30 .lpm_type("altsyncram"), 31 .numwords_a(1024), 32 .numwords_b(1024), 33 .operation_mode("DUAL_PORT"), 34 .outdata_aclr_b("NONE"), 35 .outdata_reg_b("CLOCK0"), 36 .power_up_uninitialized("FALSE"), 37 .read_during_write_mode_mixed_ports("OLD_DATA"), 38 .widthad_a(10), 39 .widthad_b(10), 40 .width_a(16), 41 .width_b(16), 42 .width_byteena_a(1)) osc_ram_unit( 43 .wren_a(wren_reg), 44 .clock0(clk), 45 .address_a(addr_reg), 46 .address_b(address), 47 .data_a(data_reg), 48 .q_b(q_wire), 49 .aclr0(1'b0), 50 .aclr1(1'b0), 51 .addressstall_a(1'b0), 52 .addressstall_b(1'b0), 53 .byteena_a(1'b1), 54 .byteena_b(1'b1), 55 .clock1(1'b1), 56 .clocken0(1'b1), 57 .clocken1(1'b1), 58 .clocken2(1'b1), 59 .clocken3(1'b1), 60 .data_b({16{1'b1}}), 61 .eccstatus(), 62 .q_a(), 63 .rden_a(1'b1), 64 .rden_b(1'b1), 65 .wren_b(1'b0)); 66 67 // body 68 always @(posedge clk) 22 23 24 reg [47:0] osc_data_reg, osc_data_next; 25 26 reg [19:0] cfg_cntr_max_reg, cfg_cntr_max_next; 27 reg [19:0] cfg_cntr_mid_reg, cfg_cntr_mid_next; 28 29 reg [2:0] int_case_reg, int_case_next; 30 31 reg int_trig_reg, int_trig_next; 32 reg [19:0] int_trig_addr_reg, int_trig_addr_next; 33 reg [19:0] int_cntr_reg, int_cntr_next; 34 35 reg [15:0] bus_mosi_reg [2:0]; 36 reg [15:0] bus_mosi_next [2:0]; 37 38 reg [15:0] bus_miso_reg, bus_miso_next; 39 reg bus_busy_reg, bus_busy_next; 40 41 reg ram_wren_reg [2:0]; 42 reg ram_wren_next [2:0]; 43 44 reg [17:0] ram_data_reg, ram_data_next; 45 reg [19:0] ram_addr_reg, ram_addr_next; 46 47 wire [17:0] ram_wren_wire; 48 49 assign ram_wren = ~ram_wren_reg[0]; 50 assign ram_addr = ram_addr_reg; 51 52 integer i; 53 genvar j; 54 55 generate 56 for (j = 0; j < 18; j = j + 1) 57 begin : SRAM_WREN 58 assign ram_wren_wire[j] = ram_wren_reg[2]; 59 assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[j] : 1'bz; 60 end 61 endgenerate 62 63 always @(posedge clock) 69 64 begin 70 65 if (reset) 71 begin 72 state_reg <= 4'b1; 73 wren_reg <= 1'b1; 74 addr_reg <= 10'd0; 75 data_reg <= 16'd0; 76 trig_reg <= 1'b0; 77 trig_addr_reg <= 10'd0; 78 counter_reg <= 10'd0; 66 begin 67 osc_data_reg <= 48'd0; 68 ram_data_reg <= 18'd0; 69 ram_addr_reg <= 20'd0; 70 bus_miso_reg <= 16'd0; 71 bus_busy_reg <= 1'b0; 72 int_case_reg <= 5'd0; 73 int_cntr_reg <= 20'd0; 74 int_trig_reg <= 1'b0; 75 int_trig_addr_reg <= 20'd0; 76 cfg_cntr_max_reg <= 20'd0; 77 cfg_cntr_mid_reg <= 20'd0; 78 79 for(i = 0; i <= 2; i = i + 1) 80 begin 81 ram_wren_reg[i] <= 1'b0; 82 bus_mosi_reg[i] <= 16'd0; 83 end 79 84 end 80 85 else 81 86 begin 82 state_reg <= state_next; 83 wren_reg <= wren_next; 84 addr_reg <= addr_next; 85 data_reg <= data_next; 86 trig_reg <= trig_next; 87 trig_addr_reg <= trig_addr_next; 88 counter_reg <= counter_next; 87 osc_data_reg <= osc_data_next; 88 ram_data_reg <= ram_data_next; 89 ram_addr_reg <= ram_addr_next; 90 bus_miso_reg <= bus_miso_next; 91 bus_busy_reg <= bus_busy_next; 92 int_case_reg <= int_case_next; 93 int_cntr_reg <= int_cntr_next; 94 int_trig_reg <= int_trig_next; 95 int_trig_addr_reg <= int_trig_addr_next; 96 cfg_cntr_max_reg <= cfg_cntr_max_next; 97 cfg_cntr_mid_reg <= cfg_cntr_mid_next; 98 99 for(i = 0; i <= 2; i = i + 1) 100 begin 101 ram_wren_reg[i] <= ram_wren_next[i]; 102 bus_mosi_reg[i] <= bus_mosi_next[i]; 103 end 89 104 end 90 105 end 106 91 107 92 108 always @* 93 109 begin 94 state_next = state_reg; 95 wren_next = wren_reg; 96 addr_next = addr_reg; 97 data_next = data_reg; 98 trig_next = trig_reg; 99 trig_addr_next = trig_addr_reg; 100 counter_next = counter_reg; 101 102 case (state_reg) 110 111 osc_data_next = osc_data_reg; 112 ram_data_next = ram_data_reg; 113 ram_addr_next = ram_addr_reg; 114 bus_miso_next = bus_miso_reg; 115 bus_busy_next = bus_busy_reg; 116 int_case_next = int_case_reg; 117 int_cntr_next = int_cntr_reg; 118 int_trig_next = int_trig_reg; 119 int_trig_addr_next = int_trig_addr_reg; 120 cfg_cntr_max_next = cfg_cntr_max_reg; 121 cfg_cntr_mid_next = cfg_cntr_mid_reg; 122 123 for(i = 0; i < 2; i = i + 1) 124 begin 125 ram_wren_next[i+1] = ram_wren_reg[i]; 126 bus_mosi_next[i+1] = bus_mosi_reg[i]; 127 end 128 ram_wren_next[0] = 1'b0; 129 bus_mosi_next[0] = 16'd0; 130 131 case (int_case_reg) 103 132 0: 104 133 begin 105 // nothing to do 106 state_next = 4'b0; 107 wren_next = 1'b0; 108 addr_next = 10'd0; 109 data_next = 16'd0; 110 counter_next = 10'd0; 111 end 112 134 ram_data_next = 18'd0; 135 ram_addr_next = 20'd0; 136 bus_busy_next = 1'b0; 137 int_cntr_next = 20'd0; 138 int_trig_next = 1'b0; 139 140 ram_data_next = {bus_mosi_reg[1][15:8], 1'b0, bus_mosi_reg[1][7:0], 1'b0}; 141 142 if (bus_ssel) 143 begin 144 bus_miso_next = {ram_data[17:10], ram_data[8:1]}; 145 ram_wren_next[0] = bus_wren; 146 if (bus_wren) 147 begin 148 ram_addr_next = bus_addr; 149 bus_mosi_next[0] = bus_mosi; 150 end 151 else 152 begin 153 // ram_addr_next = int_trig_addr_reg + bus_addr; 154 ram_addr_next = bus_addr; 155 end 156 end 157 else if (cfg_data[16]) 158 begin 159 // start recording 160 ram_wren_next[0] = 1'b1; 161 bus_busy_next = 1'b1; 162 int_case_next = 3'd1; 163 int_trig_addr_next = 20'd0; 164 cfg_cntr_max_next = {cfg_data[7:0], 10'd0}; 165 cfg_cntr_mid_next = {cfg_data[15:8], 10'd0}; 166 end 167 168 end 169 170 // sample recording 113 171 1: 114 172 begin 115 // write zeros 116 if (&addr_reg) 117 begin 118 wren_next = 1'b0; 119 state_next = 4'd2; 120 end 121 else 122 begin 123 addr_next = addr_reg + 10'd1; 124 end 125 end 126 173 ram_wren_next[0] = 1'b1; 174 if (frame) 175 begin 176 osc_data_next = osc_data; 177 ram_addr_next = ram_addr_reg + 20'd1; 178 int_case_next = 3'd2; 179 180 if ((~int_trig_reg) & (trg_flag) & 181 (int_cntr_reg == cfg_cntr_mid_reg)) 182 begin 183 int_trig_next = 1'b1; 184 int_trig_addr_next = ram_addr_reg; 185 end 186 187 if (int_trig_reg | (int_cntr_reg < cfg_cntr_mid_reg)) 188 begin 189 int_cntr_next = int_cntr_reg + 20'd1; 190 end 191 end 192 end 193 127 194 2: 128 195 begin 129 if (data_ready) 130 begin 131 wren_next = 1'b1; 132 data_next = data; 133 state_next = 4'd3; 134 end 196 ram_wren_next[0] = 1'b1; 197 ram_data_next = {osc_data_reg[15:8], 1'b0, osc_data_reg[7:0], 1'b0}; 198 ram_addr_next = ram_addr_reg + 20'd1; 199 int_case_next = 3'd3; 135 200 end 136 201 137 202 3: 138 203 begin 139 // stop write 140 wren_next = 1'b0; 141 addr_next = addr_reg + 10'd1; 142 143 if (&counter_reg) 144 begin 145 state_next = 4'd0; 146 end 147 else 148 begin 149 state_next = 4'd2; 150 151 if ((~trig_reg) & (trigger) 152 & (counter_reg == 10'd512)) 153 begin 154 // trigger 155 trig_next = 1'b1; 156 trig_addr_next = addr_reg; 157 end 158 159 if (trig_reg | (counter_reg < 10'd512)) 160 begin 161 counter_next = counter_reg + 10'd1; 162 end 163 end 164 end 165 166 default: 167 begin 168 state_next = 4'b0; 169 wren_next = 1'b0; 170 addr_next = 10'd0; 171 data_next = 16'd0; 172 counter_next = 10'd0; 173 end 204 ram_wren_next[0] = 1'b1; 205 ram_data_next = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0}; 206 ram_addr_next = ram_addr_reg + 20'd1; 207 int_case_next = 3'd4; 208 end 209 210 4: 211 begin 212 ram_wren_next[0] = 1'b1; 213 ram_data_next = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0}; 214 int_case_next = 3'd1; 215 if (int_cntr_reg >= cfg_cntr_max_reg) 216 begin 217 ram_wren_next[0] = 1'b0; 218 ram_addr_next = 20'd0; 219 int_case_next = 3'd0; 220 end 221 end 222 174 223 endcase 175 224 end 176 225 177 // output logic 178 assign q = q_wire; 179 assign start_address = trig_reg ? (trig_addr_reg ^ 10'h200) + 10'd1: addr_reg + 10'd1; 226 assign bus_miso = bus_miso_reg; 227 assign bus_busy = bus_busy_reg; 180 228 181 229 endmodule -
trunk/MultiChannelUSB/trigger.v
r83 r90 1 1 module trigger 2 2 ( 3 input wire cl k, reset,4 input wire data_ready,5 input wire [11:0] data, threshold,6 output wire tr igger3 input wire clock, frame, reset, 4 input wire [11:0] cfg_data, 5 input wire [11:0] trg_data, 6 output wire trg_flag 7 7 ); 8 8 9 reg int_trigger; 9 reg trg_flag_reg; 10 reg [11:0] cfg_data_reg; 11 reg [11:0] trg_data_reg; 10 12 11 always @(posedge cl k)13 always @(posedge clock) 12 14 begin 13 15 if (reset) 14 16 begin 15 int_trigger<= 1'b0;17 trg_flag_reg <= 1'b0; 16 18 end 17 else if (data_ready)19 else 18 20 begin 19 int_trigger <= (data >= threshold); 21 if (frame) 22 begin 23 cfg_data_reg <= cfg_data; 24 trg_data_reg <= trg_data; 25 end 26 trg_flag_reg <= (trg_data_reg >= cfg_data_reg); 20 27 end 21 28 end 22 29 23 assign tr igger = int_trigger;30 assign trg_flag = trg_flag_reg; 24 31 25 32 endmodule -
trunk/MultiChannelUSB/usb_fifo.v
r84 r90 7 7 output wire [1:0] usb_addr, 8 8 9 input wire clk, aclr,9 input wire clk, 10 10 input wire tx_wrreq, rx_rdreq, 11 11 input wire [7:0] tx_data, … … 35 35 .overflow_checking("ON"), 36 36 .underflow_checking("ON"), 37 .use_eab("O N"),37 .use_eab("OFF"), 38 38 .write_aclr_synch("OFF")) fifo_tx ( 39 .aclr( aclr),39 .aclr(1'b0), 40 40 .data(tx_data), 41 41 .rdclk(usb_clk), … … 62 62 .overflow_checking("ON"), 63 63 .underflow_checking("ON"), 64 .use_eab("O N"),64 .use_eab("OFF"), 65 65 .write_aclr_synch("OFF")) fifo_rx ( 66 .aclr( aclr),66 .aclr(1'b0), 67 67 .data(int_rx_data), 68 68 .rdclk(clk), -
trunk/MultiChannelUSB/uwt_bior31.v
r84 r90 4 4 ) 5 5 ( 6 input wire clk, reset, 7 input wire data_ready, 6 input wire clock, frame, reset, 8 7 input wire [31:0] x, 9 8 output wire [31:0] d, … … 37 36 integer i; 38 37 39 always @(posedge cl k)38 always @(posedge clock) 40 39 begin 41 40 if (reset) … … 55 54 end 56 55 end 57 else if ( data_ready)56 else if (frame) 58 57 begin 59 58 d_reg <= d_next;
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