Changeset 90 for trunk/MultiChannelUSB/Paella.v
- Timestamp:
- Feb 27, 2010, 10:10:19 PM (15 years ago)
- File:
-
- 1 edited
-
trunk/MultiChannelUSB/Paella.v (modified) (9 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/MultiChannelUSB/Paella.v
r86 r90 52 52 assign RAM_ADDR = 20'h00000; 53 53 */ 54 assign RAM_CLK = sys_cl k;54 assign RAM_CLK = sys_clock; 55 55 assign RAM_CE1 = 1'b0; 56 56 … … 73 73 74 74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend; 75 wire usb_aclr;76 75 wire usb_tx_wrreq, usb_rx_rdreq; 77 76 wire usb_tx_full, usb_rx_empty; … … 94 93 .usb_addr(usb_addr), 95 94 96 .clk(sys_clk), 97 .aclr(usb_aclr), 95 .clk(sys_clock), 98 96 99 97 .tx_full(usb_tx_full), … … 106 104 ); 107 105 108 reg bln_reset [N-1:0]; 109 wire [11:0] baseline [N-1:0]; 110 wire [11:0] bln_baseline [N-1:0]; 111 112 reg ana_reset [N-1:0]; 113 wire ana_peak_ready [N-1:0]; 114 wire ana_peak_debug [N-1:0]; 115 116 reg osc_reset [N-1:0]; 117 reg [9:0] osc_addr [N-1:0]; 118 wire [9:0] osc_start_addr [N-1:0]; 119 wire [15:0] osc_q [N-1:0]; 120 wire osc_trig [N-1:0]; 121 122 wire [3:0] osc_mux_sel [N-1:0]; 106 wire ana_good [N-1:0]; 107 wire [11:0] ana_data [N-1:0]; 108 wire [11:0] ana_base [N-1:0]; 109 123 110 wire [11:0] osc_mux_data [N-1:0]; 124 111 125 wire trg_reset [N-1:0]; 126 wire [3:0] trg_mux_sel [N-1:0]; 127 wire [11:0] trg_mux_data [N-1:0]; 128 wire [11:0] trg_thrs [N-1:0]; 129 130 reg hst_reset [N-1:0]; 131 reg [11:0] hst_addr [N-1:0]; 132 wire hst_data_ready [N-1:0]; 133 wire [11:0] hst_data [N-1:0]; 134 wire [31:0] hst_q [N-1:0]; 135 136 137 wire [3:0] hst_mux_sel [N-1:0]; 138 wire [12:0] hst_mux_data [N-1:0]; 139 140 wire [3:0] bln_mux_sel [N-1:0]; 141 wire [11:0] bln_mux_data [N-1:0]; 142 143 wire mux_reset, mux_type; 144 wire [1:0] mux_chan, mux_byte; 145 wire [15:0] mux_addr; 146 147 reg [7:0] mux_q; 148 reg [1:0] mux_max_byte; 149 reg [15:0] mux_min_addr, mux_max_addr; 112 wire [11:0] trg_mux_data; 113 wire trg_flag; 114 115 wire [83:0] int_mux_data [N-1:0]; 116 117 wire sys_clock, sys_frame; 150 118 151 119 wire [11:0] adc_data [N-1:0]; 152 153 wire data_ready;154 wire [11:0] data [N-1:0];155 120 wire [11:0] int_data [N-1:0]; 156 157 121 wire [11:0] cmp_data; 158 159 122 wire [11:0] nowhere; 160 161 wire sys_clk;162 123 163 124 wire [31:0] uwt_d1 [N-1:0]; … … 174 135 wire [1:0] uwt_flag2 [N-1:0]; 175 136 wire [1:0] uwt_flag3 [N-1:0]; 137 138 wire i2c_reset; 176 139 177 140 /* … … 179 142 .lvds_dco(ADC_DCO), 180 143 .lvds_fco(ADC_FCO), 181 .para_ data_ready(CON_CCLK[0]),144 .para_good(CON_CCLK[0]), 182 145 .para_data(CON_C[11:0]), 183 146 .adc_data(adc_data[2])); … … 191 154 */ 192 155 193 sys_pll sys_pll_unit(194 .inclk0(CLK_50MHz),195 .c0(sys_clk));196 197 156 test test_unit( 198 157 .clk(ADC_FCO), 199 .data(adc_data[2]));200 // .data(nowhere);158 // .data(adc_data[2])); 159 .data(nowhere)); 201 160 202 161 adc_lvds #( … … 207 166 .lvds_fco(ADC_FCO), 208 167 .lvds_d(ADC_D[2:0]), 209 //.adc_data({ adc_data[2],210 .adc_data({ nowhere,168 .adc_data({ adc_data[2], 169 // .adc_data({ nowhere, 211 170 adc_data[1], 212 171 adc_data[0] })); 213 214 reg [15:0] cfg_memory [31:0];215 wire [15:0] cfg_src_data;216 wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr;217 218 wire cfg_polarity [N-1:0];219 wire [ 11:0] cfg_baseline [N-1:0];220 wire [11:0] cfg_hst_threshold [N-1:0]; 221 wire [ 11:0] cfg_trg_threshold [N-1:0];172 173 assign cmp_data = CON_B[11:0]; 174 assign sys_clock = ADC_DCO; 175 assign sys_frame = ADC_FCO; 176 177 wire [15:0] cfg_bits [15:0]; 178 wire [255:0] int_cfg_bits; 179 180 wire [31:0] cfg_mux_selector; 222 181 223 182 wire cfg_reset; 224 183 225 integer j; 226 227 always @(posedge sys_clk) 228 begin 229 if (cfg_reset) 230 begin 231 for(j = 0; j <= 31; j = j + 1) 232 begin 233 cfg_memory[j] <= 16'd0; 234 end 184 wire [7:0] bus_ssel; 185 wire bus_wren; 186 wire [31:0] bus_addr; 187 wire [15:0] bus_mosi; 188 wire [15:0] bus_miso [5:0]; 189 wire [5:0] bus_busy; 190 191 wire [15:0] mrg_bus_miso; 192 wire mrg_bus_busy; 193 194 wire [79:0] int_bus_miso; 195 196 genvar j; 197 198 generate 199 for (j = 0; j < 16; j = j + 1) 200 begin : CONFIGURATION_OUTPUT 201 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16]; 235 202 end 236 else 237 begin 238 cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data; 203 endgenerate 204 205 configuration configuration_unit ( 206 .clock(sys_clock), 207 .reset(cfg_reset), 208 .bus_ssel(bus_ssel[0]), 209 .bus_wren(bus_wren), 210 .bus_addr(bus_addr[3:0]), 211 .bus_mosi(bus_mosi), 212 .bus_miso(bus_miso[0]), 213 .bus_busy(bus_busy[0]), 214 .cfg_bits(int_cfg_bits)); 215 216 generate 217 for (j = 0; j < 3; j = j + 1) 218 begin : MUX_DATA 219 assign int_mux_data[j] = { 220 {ana_good[j], 11'd0}, 221 ana_data[j], 222 ana_base[j], 223 uwt_a3[j][20:9], 224 uwt_a2[j][17:6], 225 uwt_a1[j][14:3], 226 adc_data[j]}; 239 227 end 240 end 241 242 adc_fifo #(.W(48)) adc_fifo_unit ( 243 .adc_clk(ADC_FCO), 244 .adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}), 245 .clk(sys_clk), 246 .data_ready(data_ready), 247 .data({cmp_data, int_data[2], int_data[1], int_data[0]})); 248 249 genvar i; 228 endgenerate 229 230 assign cfg_mux_selector = {cfg_bits[11], cfg_bits[10]}; 231 232 lpm_mux #( 233 .lpm_size(21), 234 .lpm_type("LPM_MUX"), 235 .lpm_width(12), 236 .lpm_widths(5)) trg_mux_unit ( 237 .sel(cfg_mux_selector[28:24]), 238 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}), 239 .result(trg_mux_data)); 250 240 251 241 generate 252 for (i = 0; i < N; i = i + 1) 253 begin : MCA_CHAIN 254 255 assign cfg_polarity[i] = cfg_memory[10][4*i]; 256 assign cfg_baseline[i] = cfg_memory[11+i][11:0]; 257 assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0]; 258 assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0]; 259 260 assign osc_mux_sel[i] = cfg_memory[20+i][3:0]; 261 assign trg_mux_sel[i] = cfg_memory[20+i][7:4]; 262 263 assign hst_mux_sel[i] = cfg_memory[23+i][3:0]; 264 assign bln_mux_sel[i] = cfg_memory[23+i][7:4]; 265 266 assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]); 267 268 uwt_bior31 #(.L(1)) uwt_1_unit ( 269 .clk(sys_clk), 270 .data_ready(data_ready), 271 .x({20'h00000, data[i]}), 272 .d(uwt_d1[i]), 273 .a(uwt_a1[i]), 274 .peak(uwt_peak1[i]), 275 .flag(uwt_flag1[i])); 276 277 uwt_bior31 #(.L(2)) uwt_2_unit ( 278 .clk(sys_clk), 279 .data_ready(data_ready), 280 .x(uwt_a1[i]), 281 .d(uwt_d2[i]), 282 .a(uwt_a2[i]), 283 .peak(uwt_peak2[i]), 284 .flag(uwt_flag2[i])); 285 286 uwt_bior31 #(.L(3)) uwt_3_unit ( 287 .clk(sys_clk), 288 .data_ready(data_ready), 289 .x(uwt_a2[i]), 290 .d(uwt_d3[i]), 291 .a(uwt_a3[i]), 292 .peak(uwt_peak3[i]), 293 .flag(uwt_flag3[i])); 294 242 for (j = 0; j < 3; j = j + 1) 243 begin : OSC_CHAIN 244 295 245 lpm_mux #( 296 .lpm_size( 7),246 .lpm_size(21), 297 247 .lpm_type("LPM_MUX"), 298 248 .lpm_width(12), 299 .lpm_widths(3)) osc_mux_unit ( 300 .sel(osc_mux_sel[i][2:0]), 301 .data({ {ana_peak_debug[i], 11'd0}, 302 hst_data[i], 303 // uwt_d3[i][11:0], 304 bln_baseline[i], 305 uwt_a3[i][20:9], 306 uwt_a2[i][17:6], 307 uwt_a1[i][14:3], 308 data[i] }), 309 .result(osc_mux_data[i])); 310 311 lpm_mux #( 312 .lpm_size(7), 313 .lpm_type("LPM_MUX"), 314 .lpm_width(12), 315 .lpm_widths(3)) trg_mux_unit ( 316 .sel(trg_mux_sel[i][2:0]), 317 .data({ {ana_peak_ready[i], 11'd0}, 318 hst_data[i], 319 // uwt_d3[i][11:0], 320 bln_baseline[i], 321 uwt_a3[i][20:9], 322 uwt_a2[i][17:6], 323 uwt_a1[i][14:3], 324 data[i] }), 325 .result(trg_mux_data[i])); 326 327 lpm_mux #( 328 .lpm_size(2), 329 .lpm_type("LPM_MUX"), 330 .lpm_width(13), 331 .lpm_widths(1)) hst_mux_unit ( 332 .sel(hst_mux_sel[i][0]), 333 .data({ {uwt_peak3[i][11:0], ana_peak_ready[i]}, 334 {data[i], data_ready} }), 335 .result(hst_mux_data[i])); 336 337 lpm_mux #( 338 .lpm_size(2), 339 .lpm_type("LPM_MUX"), 340 .lpm_width(12), 341 .lpm_widths(1)) bln_mux_unit ( 342 .sel(bln_mux_sel[i][0]), 343 .data({bln_baseline[i], cfg_baseline[i]}), 344 .result(bln_mux_data[i])); 345 346 baseline baseline_unit ( 347 .clk(sys_clk), 348 .reset(bln_reset[i]), 349 .data_ready(data_ready), 350 .uwt_flag(uwt_flag3[i]), 351 .uwt_data(uwt_peak3[i]), 352 .baseline(bln_baseline[i])); 353 354 analyser analyser_unit ( 355 .clk(sys_clk), 356 .reset(ana_reset[i]), 357 .data_ready(data_ready), 358 .uwt_flag(uwt_flag3[i]), 359 .peak_ready(ana_peak_ready[i]), 360 .peak_debug(ana_peak_debug[i])); 361 362 suppression suppression_unit ( 363 .clk(sys_clk), 364 .data(hst_mux_data[i][12:1]), 365 .baseline(bln_mux_data[i]), 366 .result(hst_data[i])); 367 368 assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]); 369 370 histogram #(.W(32)) histogram_unit ( 371 .clk(sys_clk), 372 .reset(hst_reset[i]), 373 .data_ready(hst_data_ready[i]), 374 .data(hst_data[i]), 375 .address(hst_addr[i]), 376 .q(hst_q[i])); 377 378 trigger trigger_unit ( 379 .clk(sys_clk), 380 .reset(trg_reset[i]), 381 .data_ready(data_ready), 382 .data(trg_mux_data[i]), 383 .threshold(cfg_trg_threshold[i]), 384 .trigger(osc_trig[i])); 385 386 387 oscilloscope oscilloscope_unit ( 388 .clk(sys_clk), 389 .reset(osc_reset[i]), 390 .data_ready(data_ready), 391 .data(osc_mux_data[i]), 392 .trigger(osc_trig[i]), 393 .address(osc_addr[i]), 394 .start_address(osc_start_addr[i]), 395 .q(osc_q[i])); 249 .lpm_widths(5)) osc_mux_unit ( 250 .sel(cfg_mux_selector[j*8+4:j*8]), 251 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}), 252 .result(osc_mux_data[j])); 253 396 254 end 397 255 endgenerate 398 256 399 always @* 400 begin 401 for (j = 0; j < N; j = j + 1) 402 begin 403 osc_reset[j] = 1'b0; 404 osc_addr[j] = 10'b0; 405 hst_reset[j] = 1'b0; 406 hst_addr[j] = 12'b0; 257 trigger trigger_unit ( 258 .clock(sys_clock), 259 .frame(sys_frame), 260 .reset(cfg_bits[12][14]), 261 .cfg_data(cfg_bits[12][11:0]), 262 .trg_data(trg_mux_data), 263 .trg_flag(trg_flag)); 264 265 oscilloscope oscilloscope_unit ( 266 .clock(sys_clock), 267 .frame(sys_frame), 268 .reset(cfg_bits[12][13]), 269 .cfg_data({cfg_bits[12][12], cfg_bits[13]}), 270 .trg_flag(trg_flag), 271 .osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}), 272 .ram_wren(RAM_WE), 273 .ram_addr(RAM_ADDR), 274 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}), 275 .bus_ssel(bus_ssel[1]), 276 .bus_wren(bus_wren), 277 .bus_addr(bus_addr[19:0]), 278 .bus_mosi(bus_mosi), 279 .bus_miso(bus_miso[1]), 280 .bus_busy(bus_busy[1])); 281 282 generate 283 for (j = 0; j < 3; j = j + 1) 284 begin : MCA_CHAIN 285 286 assign int_data[j] = (cfg_bits[0][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]); 287 288 uwt_bior31 #(.L(1)) uwt_1_unit ( 289 .clock(sys_clock), 290 .frame(sys_frame), 291 .reset(1'b0), 292 .x({20'h00000, int_data[j]}), 293 .d(uwt_d1[j]), 294 .a(uwt_a1[j]), 295 .peak(uwt_peak1[j]), 296 .flag(uwt_flag1[j])); 297 298 uwt_bior31 #(.L(2)) uwt_2_unit ( 299 .clock(sys_clock), 300 .frame(sys_frame), 301 .reset(1'b0), 302 .x(uwt_a1[j]), 303 .d(uwt_d2[j]), 304 .a(uwt_a2[j]), 305 .peak(uwt_peak2[j]), 306 .flag(uwt_flag2[j])); 307 308 uwt_bior31 #(.L(3)) uwt_3_unit ( 309 .clock(sys_clock), 310 .frame(sys_frame), 311 .reset(1'b0), 312 .x(uwt_a2[j]), 313 .d(uwt_d3[j]), 314 .a(uwt_a3[j]), 315 .peak(uwt_peak3[j]), 316 .flag(uwt_flag3[j])); 317 318 analyser analyser_unit ( 319 .clock(sys_clock), 320 .frame(sys_frame), 321 .reset(cfg_bits[2+2*j][12]), 322 .cfg_data({cfg_bits[2+2*j][11:0], cfg_bits[1+2*j][12:0]}), 323 .uwt_flag(uwt_flag3[j]), 324 .uwt_data(uwt_peak3[j]), 325 .ana_good(ana_good[j]), 326 .ana_data(ana_data[j]), 327 .ana_base(ana_base[j])); 328 329 histogram histogram_unit ( 330 .clock(sys_clock), 331 .frame(sys_frame), 332 .reset(cfg_bits[7+j][13]), 333 .cfg_data(cfg_bits[7+j][12:0]), 334 .hst_good(ana_good[j]), 335 .hst_data(ana_data[j]), 336 .bus_ssel(bus_ssel[2+j]), 337 .bus_wren(bus_wren), 338 .bus_addr(bus_addr[12:0]), 339 .bus_mosi(bus_mosi), 340 .bus_miso(bus_miso[2+j]), 341 .bus_busy(bus_busy[2+j])); 342 407 343 end 408 409 case(mux_type) 410 1'b0: 411 begin 412 osc_reset[mux_chan] = mux_reset; 413 osc_addr[mux_chan] = mux_addr[9:0]; 414 mux_max_byte = 2'd1; 415 mux_min_addr = {6'd0, osc_start_addr[mux_chan]}; 416 mux_max_addr = 16'd1023; 417 end 418 419 1'b1: 420 begin 421 hst_reset[mux_chan] = mux_reset; 422 hst_addr[mux_chan] = mux_addr[11:0]; 423 mux_max_byte = 2'd3; 424 mux_min_addr = 16'd0; 425 mux_max_addr = 16'd4095; 426 end 427 endcase 428 end 429 430 always @* 431 begin 432 case ({mux_type, mux_byte}) 433 3'b000: mux_q = osc_q[mux_chan][7:0]; 434 3'b001: mux_q = osc_q[mux_chan][15:8]; 435 436 3'b100: mux_q = hst_q[mux_chan][7:0]; 437 3'b101: mux_q = hst_q[mux_chan][15:8]; 438 3'b110: mux_q = hst_q[mux_chan][23:16]; 439 3'b111: mux_q = hst_q[mux_chan][31:24]; 440 441 default: mux_q = 8'd0; 442 endcase 443 end 444 445 wire i2c_aclr; 446 wire i2c_wrreq; 447 wire i2c_full; 448 wire [15:0] i2c_data; 344 endgenerate 449 345 450 346 i2c_fifo i2c_unit( 451 .clk(sys_clk), 452 .aclr(i2c_aclr), 453 .wrreq(i2c_wrreq), 454 .data(i2c_data), 455 .full(i2c_full), 347 .clock(sys_clock), 348 .reset(i2c_reset), 456 349 /* 457 350 normal connection … … 462 355 */ 463 356 .i2c_sda(I2C_SCL), 464 .i2c_scl(I2C_SDA)); 357 .i2c_scl(I2C_SDA), 358 359 .bus_ssel(bus_ssel[5]), 360 .bus_wren(bus_wren), 361 .bus_mosi(bus_mosi), 362 .bus_busy(bus_busy[5])); 363 364 generate 365 for (j = 0; j < 5; j = j + 1) 366 begin : BUS_OUTPUT 367 assign int_bus_miso[j*16+15:j*16] = bus_miso[j]; 368 end 369 endgenerate 370 371 lpm_mux #( 372 .lpm_size(5), 373 .lpm_type("LPM_MUX"), 374 .lpm_width(16), 375 .lpm_widths(3)) bus_miso_mux_unit ( 376 .sel(bus_addr[30:28]), 377 .data(int_bus_miso), 378 .result(mrg_bus_miso)); 379 380 lpm_mux #( 381 .lpm_size(6), 382 .lpm_type("LPM_MUX"), 383 .lpm_width(1), 384 .lpm_widths(3)) bus_busy_mux_unit ( 385 .sel(bus_addr[30:28]), 386 .data(bus_busy), 387 .result(mrg_bus_busy)); 388 389 /* 390 lpm_or #( 391 .lpm_size(6), 392 .lpm_type("LPM_OR"), 393 .lpm_width(16)) bus_miso_or_unit ( 394 .data(int_bus_miso), 395 .result(mrg_bus_miso)); 396 */ 397 398 lpm_decode #( 399 .lpm_decodes(8), 400 .lpm_type("LPM_DECODE"), 401 .lpm_width(3)) lpm_decode_unit ( 402 .data(bus_addr[30:28]), 403 .eq(bus_ssel), 404 .aclr(), 405 .clken(), 406 .clock(), 407 .enable()); 465 408 466 409 control control_unit ( 467 .clk(sys_clk), 468 .cfg_reset(cfg_reset), 469 .cfg_src_data(cfg_memory[cfg_src_addr[4:0]]), 470 .cfg_src_addr(cfg_src_addr), 471 .cfg_dst_data(cfg_dst_data), 472 .cfg_dst_addr(cfg_dst_addr), 410 .clock(sys_clock), 473 411 .rx_empty(usb_rx_empty), 474 412 .tx_full(usb_tx_full), 475 413 .rx_data(usb_rx_data), 476 .mux_max_byte(mux_max_byte),477 .mux_min_addr(mux_min_addr),478 .mux_max_addr(mux_max_addr),479 .mux_q(mux_q),480 .mux_reset(mux_reset),481 .mux_type(mux_type),482 .mux_chan(mux_chan),483 .mux_byte(mux_byte),484 .mux_addr(mux_addr),485 414 .rx_rdreq(usb_rx_rdreq), 486 415 .tx_wrreq(usb_tx_wrreq), 487 416 .tx_data(usb_tx_data), 488 .ram_we(RAM_WE), 489 .ram_addr(RAM_ADDR), 490 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}), 491 .ept_data_ready(data_ready), 492 .ept_data({cmp_data, data[2], data[1], data[0]}), 493 .i2c_wrreq(i2c_wrreq), 494 .i2c_data(i2c_data), 495 .i2c_full(i2c_full), 417 .bus_wren(bus_wren), 418 .bus_addr(bus_addr), 419 .bus_mosi(bus_mosi), 420 .bus_miso(mrg_bus_miso), 421 .bus_busy(mrg_bus_busy), 496 422 .led(LED)); 497 423
Note:
See TracChangeset
for help on using the changeset viewer.
