Changeset 101 for trunk/MultiChannelUSB/Paella.v
- Timestamp:
- Mar 12, 2010, 11:59:48 AM (14 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/Paella.v
r90 r101 104 104 ); 105 105 106 wire ana_dead [N-1:0]; 106 107 wire ana_good [N-1:0]; 107 108 wire [11:0] ana_data [N-1:0]; 108 109 wire [11:0] ana_base [N-1:0]; 109 110 111 wire cnt_good [N-1:0]; 112 110 113 wire [11:0] osc_mux_data [N-1:0]; 111 114 … … 119 122 wire [11:0] adc_data [N-1:0]; 120 123 wire [11:0] int_data [N-1:0]; 124 wire [11:0] sys_data [N-1:0]; 121 125 wire [11:0] cmp_data; 122 126 wire [11:0] nowhere; … … 146 150 .adc_data(adc_data[2])); 147 151 */ 148 /*152 149 153 wire adc_pll_clk; 150 154 155 /* 151 156 adc_pll adc_pll_unit( 152 157 .inclk0(ADC_FCO), … … 154 159 */ 155 160 161 sys_pll sys_pll_unit( 162 .inclk0(CLK_50MHz), 163 .c0(sys_clock)); 164 156 165 test test_unit( 157 166 .clk(ADC_FCO), 158 //.data(adc_data[2]));159 .data(nowhere));167 .data(adc_data[2])); 168 // .data(nowhere)); 160 169 161 170 adc_lvds #( … … 166 175 .lvds_fco(ADC_FCO), 167 176 .lvds_d(ADC_D[2:0]), 168 .adc_data({ adc_data[2],169 //.adc_data({ nowhere,177 // .adc_data({ adc_data[2], 178 .adc_data({ nowhere, 170 179 adc_data[1], 171 180 adc_data[0] })); 172 181 182 /* 173 183 assign cmp_data = CON_B[11:0]; 174 184 assign sys_clock = ADC_DCO; 175 185 assign sys_frame = ADC_FCO; 176 177 wire [15:0] cfg_bits [15:0]; 178 wire [255:0] int_cfg_bits; 186 */ 187 188 wire [15:0] cfg_bits [31:0]; 189 wire [511:0] int_cfg_bits; 179 190 180 191 wire [31:0] cfg_mux_selector; … … 182 193 wire cfg_reset; 183 194 184 wire [ 7:0] bus_ssel;195 wire [8:0] bus_ssel; 185 196 wire bus_wren; 186 197 wire [31:0] bus_addr; 187 198 wire [15:0] bus_mosi; 188 wire [15:0] bus_miso [ 5:0];189 wire [ 5:0] bus_busy;199 wire [15:0] bus_miso [7:0]; 200 wire [8:0] bus_busy; 190 201 191 202 wire [15:0] mrg_bus_miso; 192 203 wire mrg_bus_busy; 193 204 194 wire [ 79:0] int_bus_miso;205 wire [127:0] int_bus_miso; 195 206 196 207 genvar j; 197 208 198 209 generate 199 for (j = 0; j < 16; j = j + 1)210 for (j = 0; j < 32; j = j + 1) 200 211 begin : CONFIGURATION_OUTPUT 201 212 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16]; … … 208 219 .bus_ssel(bus_ssel[0]), 209 220 .bus_wren(bus_wren), 210 .bus_addr(bus_addr[ 3:0]),221 .bus_addr(bus_addr[4:0]), 211 222 .bus_mosi(bus_mosi), 212 223 .bus_miso(bus_miso[0]), … … 224 235 uwt_a2[j][17:6], 225 236 uwt_a1[j][14:3], 226 adc_data[j]};237 sys_data[j]}; 227 238 end 228 239 endgenerate 229 240 230 assign cfg_mux_selector = {cfg_bits[ 11], cfg_bits[10]};241 assign cfg_mux_selector = {cfg_bits[3], cfg_bits[2]}; 231 242 232 243 lpm_mux #( … … 258 269 .clock(sys_clock), 259 270 .frame(sys_frame), 260 .reset(cfg_bits[ 12][14]),261 .cfg_data(cfg_bits[ 12][11:0]),271 .reset(cfg_bits[0][0]), 272 .cfg_data(cfg_bits[5][11:0]), 262 273 .trg_data(trg_mux_data), 263 274 .trg_flag(trg_flag)); … … 266 277 .clock(sys_clock), 267 278 .frame(sys_frame), 268 .reset(cfg_bits[ 12][13]),269 .cfg_data( {cfg_bits[12][12], cfg_bits[13]}),279 .reset(cfg_bits[0][1]), 280 .cfg_data(cfg_bits[4][0]), 270 281 .trg_flag(trg_flag), 271 282 .osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}), … … 280 291 .bus_busy(bus_busy[1])); 281 292 293 294 adc_fifo #(.W(48)) adc_fifo_unit ( 295 .adc_clock(ADC_FCO), 296 .adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}), 297 .sys_clock(sys_clock), 298 .sys_frame(sys_frame), 299 .sys_data({cmp_data, int_data[2], int_data[1], int_data[0]})); 300 301 282 302 generate 283 303 for (j = 0; j < 3; j = j + 1) 284 304 begin : MCA_CHAIN 285 305 286 assign int_data[j] = (cfg_bits[0][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);306 assign sys_data[j] = (cfg_bits[1][4*j]) ? (int_data[j] ^ 12'hfff) : (int_data[j]); 287 307 288 308 uwt_bior31 #(.L(1)) uwt_1_unit ( … … 290 310 .frame(sys_frame), 291 311 .reset(1'b0), 292 .x({20'h00000, int_data[j]}),312 .x({20'h00000, sys_data[j]}), 293 313 .d(uwt_d1[j]), 294 314 .a(uwt_a1[j]), … … 319 339 .clock(sys_clock), 320 340 .frame(sys_frame), 321 .reset(cfg_bits[ 2+2*j][12]),322 .cfg_data({cfg_bits[ 2+2*j][11:0], cfg_bits[1+2*j][12:0]}),341 .reset(cfg_bits[0][2+j]), 342 .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}), 323 343 .uwt_flag(uwt_flag3[j]), 324 344 .uwt_data(uwt_peak3[j]), 345 .ana_dead(ana_dead[j]), 325 346 .ana_good(ana_good[j]), 326 347 .ana_data(ana_data[j]), … … 330 351 .clock(sys_clock), 331 352 .frame(sys_frame), 332 .reset(cfg_bits[7+j][13]), 333 .cfg_data(cfg_bits[7+j][12:0]), 334 .hst_good(ana_good[j]), 353 .reset(cfg_bits[0][5+j]), 354 .hst_good((ana_good[j]) & (cnt_good[j])), 335 355 .hst_data(ana_data[j]), 336 356 .bus_ssel(bus_ssel[2+j]), … … 341 361 .bus_busy(bus_busy[2+j])); 342 362 363 counter counter_unit ( 364 .clock(sys_clock), 365 .frame((sys_frame) & (~ana_dead[j])), 366 .reset(cfg_bits[0][8+j]), 367 .cfg_data(cfg_bits[12+j]), 368 .bus_ssel(bus_ssel[5+j]), 369 .bus_wren(bus_wren), 370 .bus_addr(bus_addr[1:0]), 371 .bus_mosi(bus_mosi), 372 .bus_miso(bus_miso[5+j]), 373 .bus_busy(bus_busy[5+j]), 374 .cnt_good(cnt_good[j])); 375 343 376 end 344 377 endgenerate … … 357 390 .i2c_scl(I2C_SDA), 358 391 359 .bus_ssel(bus_ssel[ 5]),392 .bus_ssel(bus_ssel[8]), 360 393 .bus_wren(bus_wren), 361 394 .bus_mosi(bus_mosi), 362 .bus_busy(bus_busy[ 5]));395 .bus_busy(bus_busy[8])); 363 396 364 397 generate 365 for (j = 0; j < 5; j = j + 1)398 for (j = 0; j < 8; j = j + 1) 366 399 begin : BUS_OUTPUT 367 400 assign int_bus_miso[j*16+15:j*16] = bus_miso[j]; … … 370 403 371 404 lpm_mux #( 372 .lpm_size( 5),405 .lpm_size(8), 373 406 .lpm_type("LPM_MUX"), 374 407 .lpm_width(16), … … 379 412 380 413 lpm_mux #( 381 .lpm_size( 6),414 .lpm_size(9), 382 415 .lpm_type("LPM_MUX"), 383 416 .lpm_width(1), 384 .lpm_widths( 3)) bus_busy_mux_unit (385 .sel(bus_addr[3 0:28]),417 .lpm_widths(4)) bus_busy_mux_unit ( 418 .sel(bus_addr[31:28]), 386 419 .data(bus_busy), 387 420 .result(mrg_bus_busy)); … … 397 430 398 431 lpm_decode #( 399 .lpm_decodes( 8),432 .lpm_decodes(9), 400 433 .lpm_type("LPM_DECODE"), 401 .lpm_width( 3)) lpm_decode_unit (402 .data(bus_addr[3 0:28]),434 .lpm_width(4)) lpm_decode_unit ( 435 .data(bus_addr[31:28]), 403 436 .eq(bus_ssel), 404 437 .aclr(),
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