Changeset 159 for trunk/MultiChannelUSB/Paella.v
- Timestamp:
- Jan 11, 2012, 4:32:57 PM (13 years ago)
- File:
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- 1 edited
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trunk/MultiChannelUSB/Paella.v
r101 r159 8 8 inout wire I2C_SCL, 9 9 inout wire [4:0] CON_A, 10 input wire [1 5:0] CON_B,10 input wire [16:0] CON_B, 11 11 input wire [12:0] CON_C, 12 input wire [1:0]CON_BCLK,12 input wire CON_BCLK, 13 13 input wire [1:0] CON_CCLK, 14 14 … … 68 68 69 69 assign USB_PA2 = ~usb_rden; 70 assign USB_PA4 = usb_addr[0]; 71 assign USB_PA5 = usb_addr[1]; 70 assign USB_PA5 = 1'b1; 72 71 assign USB_PA6 = ~usb_pktend; 73 72 … … 76 75 wire usb_tx_full, usb_rx_empty; 77 76 wire [7:0] usb_tx_data, usb_rx_data; 78 wire [1:0] usb_addr;79 77 80 78 assign USB_SLRD = ~usb_rdreq; … … 83 81 usb_fifo usb_unit 84 82 ( 85 .usb_cl k(USB_IFCLK),83 .usb_clock(USB_IFCLK), 86 84 .usb_data(USB_PB), 87 85 .usb_full(~USB_FLAGB), … … 91 89 .usb_rden(usb_rden), 92 90 .usb_pktend(usb_pktend), 93 .usb_addr( usb_addr),94 95 .cl k(sys_clock),91 .usb_addr(USB_PA4), 92 93 .clock(sys_clock), 96 94 97 95 .tx_full(usb_tx_full), … … 103 101 .rx_q(usb_rx_data) 104 102 ); 105 106 wire ana_dead [N-1:0];107 wire ana_good [N-1:0];108 wire [11:0] ana_data [N-1:0];109 wire [11:0] ana_base [N-1:0];110 111 wire cnt_good [N-1:0];112 113 wire [11:0] osc_mux_data [ N-1:0];103 /* 104 reg [31:0] led_counter; 105 always @(posedge CLK_50MHz) 106 begin 107 led_counter = led_counter + 32'd1; 108 end 109 assign LED = led_counter[28]; 110 */ 111 wire [11:0] osc_mux_data [4:0]; 114 112 115 113 wire [11:0] trg_mux_data; 116 114 wire trg_flag; 117 115 118 wire [83:0] int_mux_data [N-1:0]; 116 wire [4*12-1:0] int_mux_data [N-1:0]; 117 118 wire [1:0] amp_flag [2*N-1:0]; 119 wire [11:0] amp_data [2*N-1:0]; 120 121 wire cnt_good [N-1:0]; 122 wire [15:0] cnt_bits_wire; 119 123 120 124 wire sys_clock, sys_frame; 121 125 122 wire [11:0] adc_data [N-1:0]; 123 wire [11:0] int_data [N-1:0]; 126 wire [11:0] adc_data [N-1:0]; 124 127 wire [11:0] sys_data [N-1:0]; 125 wire [11:0] cmp_data; 126 wire [11:0] nowhere; 127 128 wire [31:0] uwt_d1 [N-1:0]; 129 wire [31:0] uwt_a1 [N-1:0]; 130 wire [31:0] uwt_peak1 [N-1:0]; 131 wire [31:0] uwt_d2 [N-1:0]; 132 wire [31:0] uwt_a2 [N-1:0]; 133 wire [31:0] uwt_peak2 [N-1:0]; 134 wire [31:0] uwt_d3 [N-1:0]; 135 wire [31:0] uwt_a3 [N-1:0]; 136 wire [31:0] uwt_peak3 [N-1:0]; 137 138 wire [1:0] uwt_flag1 [N-1:0]; 139 wire [1:0] uwt_flag2 [N-1:0]; 140 wire [1:0] uwt_flag3 [N-1:0]; 141 128 wire [11:0] tst_data; 129 130 wire [1:0] cmp_data; 131 wire [1:0] del_data; 132 133 wire [19:0] cic_data [N-1:0]; 134 135 wire [11:0] dec_data [N-1:0]; 136 wire [11:0] clp_data [N-1:0]; 137 wire [11:0] tmp_data; 138 139 142 140 wire i2c_reset; 143 144 /*145 adc_para adc_para_unit (146 .lvds_dco(ADC_DCO),147 .lvds_fco(ADC_FCO),148 .para_good(CON_CCLK[0]),149 .para_data(CON_C[11:0]),150 .adc_data(adc_data[2]));151 */152 153 wire adc_pll_clk;154 155 /*156 adc_pll adc_pll_unit(157 .inclk0(ADC_FCO),158 .c0(adc_pll_clk));159 */160 141 161 142 sys_pll sys_pll_unit( … … 165 146 test test_unit( 166 147 .clk(ADC_FCO), 167 .data(adc_data[2])); 168 // .data(nowhere)); 148 .data(tst_data)); 169 149 170 150 adc_lvds #( 171 151 .size(3), 172 152 .width(12)) adc_lvds_unit ( 153 .clock(sys_clock), 173 154 .lvds_dco(ADC_DCO), 174 // .lvds_dco(adc_pll_clk),175 155 .lvds_fco(ADC_FCO), 176 .lvds_d(ADC_D[2:0]), 177 // .adc_data({ adc_data[2], 178 .adc_data({ nowhere, 179 adc_data[1], 180 adc_data[0] })); 181 182 /* 183 assign cmp_data = CON_B[11:0]; 184 assign sys_clock = ADC_DCO; 185 assign sys_frame = ADC_FCO; 186 */ 187 188 wire [15:0] cfg_bits [31:0]; 189 wire [511:0] int_cfg_bits; 190 191 wire [31:0] cfg_mux_selector; 156 .lvds_d(ADC_D), 157 .trig(TRG[1:0]), 158 .adc_frame(sys_frame), 159 .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]})); 160 161 wire [15:0] cfg_bits [63:0]; 162 wire [1023:0] int_cfg_bits; 163 164 wire [39:0] cfg_mux_selector; 192 165 193 166 wire cfg_reset; 194 167 195 wire [ 8:0] bus_ssel;168 wire [11:0] bus_ssel; 196 169 wire bus_wren; 197 170 wire [31:0] bus_addr; 198 171 wire [15:0] bus_mosi; 199 wire [15:0] bus_miso [ 7:0];200 wire [ 8:0] bus_busy;172 wire [15:0] bus_miso [10:0]; 173 wire [11:0] bus_busy; 201 174 202 175 wire [15:0] mrg_bus_miso; 203 176 wire mrg_bus_busy; 204 177 205 wire [1 27:0] int_bus_miso;178 wire [11*16-1:0] int_bus_miso; 206 179 207 180 genvar j; 208 181 209 182 generate 210 for (j = 0; j < 32; j = j + 1)183 for (j = 0; j < 64; j = j + 1) 211 184 begin : CONFIGURATION_OUTPUT 212 185 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16]; … … 229 202 begin : MUX_DATA 230 203 assign int_mux_data[j] = { 231 {ana_good[j], 11'd0}, 232 ana_data[j], 233 ana_base[j], 234 uwt_a3[j][20:9], 235 uwt_a2[j][17:6], 236 uwt_a1[j][14:3], 204 {4'd0, amp_flag[0+2*j][0], 7'd0}, 205 amp_data[0+2*j], 206 clp_data[j], 237 207 sys_data[j]}; 238 208 end 239 209 endgenerate 240 210 241 assign cfg_mux_selector = {cfg_bits[ 3], cfg_bits[2]};211 assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]}; 242 212 243 213 lpm_mux #( 244 .lpm_size( 21),214 .lpm_size(4*3), 245 215 .lpm_type("LPM_MUX"), 246 216 .lpm_width(12), 247 .lpm_widths( 5)) trg_mux_unit (248 .sel(cfg_ mux_selector[28:24]),217 .lpm_widths(4)) trg_mux_unit ( 218 .sel(cfg_bits[4][11:8]), 249 219 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}), 250 220 .result(trg_mux_data)); 251 221 252 222 generate 253 for (j = 0; j < 3; j = j + 1)223 for (j = 0; j < 5; j = j + 1) 254 224 begin : OSC_CHAIN 255 225 256 226 lpm_mux #( 257 .lpm_size( 21),227 .lpm_size(4*3), 258 228 .lpm_type("LPM_MUX"), 259 229 .lpm_width(12), 260 .lpm_widths( 5)) osc_mux_unit (261 .sel(cfg_mux_selector[j*8+ 4:j*8]),230 .lpm_widths(4)) osc_mux_unit ( 231 .sel(cfg_mux_selector[j*8+3:j*8]), 262 232 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}), 263 233 .result(osc_mux_data[j])); … … 278 248 .frame(sys_frame), 279 249 .reset(cfg_bits[0][1]), 280 .cfg_data(cfg_bits[ 4][0]),250 .cfg_data(cfg_bits[5][12]), 281 251 .trg_flag(trg_flag), 282 .osc_data({ cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),252 .osc_data({2'd0, cmp_data, osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}), 283 253 .ram_wren(RAM_WE), 284 254 .ram_addr(RAM_ADDR), … … 291 261 .bus_busy(bus_busy[1])); 292 262 293 294 adc_fifo #(.W(48)) adc_fifo_unit ( 295 .adc_clock(ADC_FCO), 296 .adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}), 297 .sys_clock(sys_clock), 298 .sys_frame(sys_frame), 299 .sys_data({cmp_data, int_data[2], int_data[1], int_data[0]})); 300 301 263 filter #(.size(3), .width(12)) filter_unit ( 264 .clock(sys_clock), 265 .frame(sys_frame), 266 .reset(1'b0), 267 .inp_data({sys_data[2], sys_data[1], sys_data[0]}), 268 .out_data({cic_data[2], cic_data[1], cic_data[0]})); 269 270 271 /* 272 clip #(.shift(19), .width(19), .widthr(12)) clip_unit ( 273 .clock(sys_clock), 274 .frame(sys_frame), 275 .reset(1'b0), 276 .del_data({cfg_bits[39][5:0], cfg_bits[37][5:0], cfg_bits[35+8][5:0], cfg_bits[33][5:0]}), 277 .amp_data({6'd6, 6'd6, 6'd6, 6'd6}), 278 .tau_data({cfg_bits[38], cfg_bits[36], cfg_bits[34], cfg_bits[32]}), 279 .inp_data({ 280 19'd0, cic_data[2][18:0], 281 cic_data[1][18:0], cic_data[0][18:0]}), 282 .out_data({ 283 tmp_data, clp_data[2], 284 clp_data[1], clp_data[0]})); 285 */ 302 286 generate 303 287 for (j = 0; j < 3; j = j + 1) 304 288 begin : MCA_CHAIN 305 306 assign sys_data[j] = (cfg_bits[1][4*j]) ? (int_data[j] ^ 12'hfff) : (int_data[j]); 307 308 uwt_bior31 #(.L(1)) uwt_1_unit ( 289 290 shift #(.shift(9), .width(19), .widthr(12)) shift_unit ( 309 291 .clock(sys_clock), 310 292 .frame(sys_frame), 311 293 .reset(1'b0), 312 . x({20'h00000, sys_data[j]}),313 . d(uwt_d1[j]),314 . a(uwt_a1[j]),315 .peak(uwt_peak1[j]),316 .flag(uwt_flag1[j]));317 318 uwt_bior31 #(.L(2)) uwt_2_unit(294 .amp_data(6'd5), 295 .inp_data(cic_data[j][18:0]), 296 .out_data(clp_data[j])); 297 298 assign sys_data[j] = (cfg_bits[1][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]); 299 300 amplitude #(.width(12)) amplitude_unit_1 ( 319 301 .clock(sys_clock), 320 302 .frame(sys_frame), 321 303 .reset(1'b0), 322 .x(uwt_a1[j]), 323 .d(uwt_d2[j]), 324 .a(uwt_a2[j]), 325 .peak(uwt_peak2[j]), 326 .flag(uwt_flag2[j])); 327 328 uwt_bior31 #(.L(3)) uwt_3_unit ( 304 .cfg_data(cfg_bits[6+2*j][11:0]), 305 .inp_data(clp_data[j]), 306 .out_flag(amp_flag[0+2*j]), 307 .out_data(amp_data[0+2*j])); 308 309 amplitude #(.width(12)) amplitude_unit_2 ( 329 310 .clock(sys_clock), 330 311 .frame(sys_frame), 331 312 .reset(1'b0), 332 .x(uwt_a2[j]), 333 .d(uwt_d3[j]), 334 .a(uwt_a3[j]), 335 .peak(uwt_peak3[j]), 336 .flag(uwt_flag3[j])); 337 338 analyser analyser_unit ( 339 .clock(sys_clock), 340 .frame(sys_frame), 341 .reset(cfg_bits[0][2+j]), 342 .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}), 343 .uwt_flag(uwt_flag3[j]), 344 .uwt_data(uwt_peak3[j]), 345 .ana_dead(ana_dead[j]), 346 .ana_good(ana_good[j]), 347 .ana_data(ana_data[j]), 348 .ana_base(ana_base[j])); 349 350 histogram histogram_unit ( 351 .clock(sys_clock), 352 .frame(sys_frame), 353 .reset(cfg_bits[0][5+j]), 354 .hst_good((ana_good[j]) & (cnt_good[j])), 355 .hst_data(ana_data[j]), 356 .bus_ssel(bus_ssel[2+j]), 357 .bus_wren(bus_wren), 358 .bus_addr(bus_addr[12:0]), 359 .bus_mosi(bus_mosi), 360 .bus_miso(bus_miso[2+j]), 361 .bus_busy(bus_busy[2+j])); 362 363 counter counter_unit ( 364 .clock(sys_clock), 365 .frame((sys_frame) & (~ana_dead[j])), 366 .reset(cfg_bits[0][8+j]), 367 .cfg_data(cfg_bits[12+j]), 368 .bus_ssel(bus_ssel[5+j]), 369 .bus_wren(bus_wren), 370 .bus_addr(bus_addr[1:0]), 371 .bus_mosi(bus_mosi), 372 .bus_miso(bus_miso[5+j]), 373 .bus_busy(bus_busy[5+j]), 374 .cnt_good(cnt_good[j])); 313 .cfg_data(cfg_bits[7+2*j][11:0]), 314 .inp_data(clp_data[j]), 315 .out_flag(amp_flag[1+2*j]), 316 .out_data(amp_data[1+2*j])); 375 317 376 318 end 377 319 endgenerate 320 321 histogram32 histogram32_unit ( 322 .clock(sys_clock), 323 .frame(sys_frame), 324 .reset(cfg_bits[0][5]), 325 .hst_good((amp_flag[0][0]) & (cnt_good[0]) & (cfg_bits[13][1])), 326 .hst_data(amp_data[0]), 327 /* 328 .hst_good((amp_flag[j]) & (cnt_good[j]) & (cfg_bits[13][1])), 329 .hst_data(amp_data[j]), 330 */ 331 .bus_ssel(bus_ssel[2]), 332 .bus_wren(bus_wren), 333 .bus_addr(bus_addr[12:0]), 334 .bus_mosi(bus_mosi), 335 .bus_miso(bus_miso[2]), 336 .bus_busy(bus_busy[2])); 337 338 counter hst_counter_unit ( 339 .clock(sys_clock), 340 .frame((sys_frame) & (~amp_flag[0][1])), 341 // .frame(sys_frame), 342 .reset(cfg_bits[0][8]), 343 .setup(cfg_bits[13][0]), 344 .count(cfg_bits[13][1]), 345 .bus_ssel(bus_ssel[5]), 346 .bus_wren(bus_wren), 347 .bus_addr(bus_addr[1:0]), 348 .bus_mosi(bus_mosi), 349 .bus_miso(bus_miso[5]), 350 .bus_busy(bus_busy[5]), 351 .cnt_good(cnt_good[0])); 352 353 histogram16 histogram16_unit ( 354 .clock(sys_clock), 355 .frame(sys_frame), 356 .reset(cfg_bits[0][11]), 357 .hst_good((cnt_good[2]) & (~cnt_good[1])), 358 .hst_data(cnt_bits_wire), 359 .bus_ssel(bus_ssel[8]), 360 .bus_wren(bus_wren), 361 .bus_addr(bus_addr[13:0]), 362 .bus_mosi(bus_mosi), 363 .bus_miso(bus_miso[8]), 364 .bus_busy(bus_busy[8])); 365 366 counter rmt_counter_1 ( 367 .clock(sys_clock), 368 .frame((sys_frame) & (~amp_flag[1][1])), 369 // .frame(sys_frame), 370 .reset(cfg_bits[0][12]), 371 .setup((sys_frame) & (~cnt_good[1])), 372 .count((cnt_good[2]) & (cfg_bits[16][1])), 373 .bus_ssel(bus_ssel[9]), 374 .bus_wren(bus_wren), 375 .bus_addr(bus_addr[1:0]), 376 .bus_mosi(bus_mosi), 377 .bus_miso(bus_miso[9]), 378 .bus_busy(bus_busy[9]), 379 .cnt_good(cnt_good[1])); 380 381 counter rmt_counter_2 ( 382 .clock(sys_clock), 383 .frame((sys_frame) & (~cnt_good[1])), 384 .reset(cfg_bits[0][13]), 385 .setup(cfg_bits[16][0]), 386 .count(cfg_bits[16][1]), 387 .bus_ssel(bus_ssel[10]), 388 .bus_wren(bus_wren), 389 .bus_addr(bus_addr[1:0]), 390 .bus_mosi(bus_mosi), 391 .bus_miso(bus_miso[10]), 392 .bus_busy(bus_busy[10]), 393 .cnt_good(cnt_good[2])); 394 395 lpm_counter #( 396 .lpm_direction("UP"), 397 .lpm_port_updown("PORT_UNUSED"), 398 .lpm_type("LPM_COUNTER"), 399 .lpm_width(16)) lpm_counter_component ( 400 .sclr(((sys_frame) & (cnt_good[2]) & (~cnt_good[1])) | (cfg_bits[0][11])), 401 .clock(sys_clock), 402 .cnt_en((sys_frame) & (amp_flag[1][0]) & (cnt_good[1]) & (cnt_good[2]) & (cfg_bits[16][1])), 403 .q(cnt_bits_wire)); 378 404 379 405 i2c_fifo i2c_unit( … … 390 416 .i2c_scl(I2C_SDA), 391 417 392 .bus_ssel(bus_ssel[ 8]),393 .bus_wren(bus_wren), 394 .bus_mosi(bus_mosi), 395 .bus_busy(bus_busy[ 8]));418 .bus_ssel(bus_ssel[11]), 419 .bus_wren(bus_wren), 420 .bus_mosi(bus_mosi), 421 .bus_busy(bus_busy[11])); 396 422 397 423 generate 398 for (j = 0; j < 8; j = j + 1)424 for (j = 0; j < 11; j = j + 1) 399 425 begin : BUS_OUTPUT 400 426 assign int_bus_miso[j*16+15:j*16] = bus_miso[j]; … … 403 429 404 430 lpm_mux #( 405 .lpm_size( 8),431 .lpm_size(11), 406 432 .lpm_type("LPM_MUX"), 407 433 .lpm_width(16), 408 .lpm_widths( 3)) bus_miso_mux_unit (409 .sel(bus_addr[3 0:28]),434 .lpm_widths(4)) bus_miso_mux_unit ( 435 .sel(bus_addr[31:28]), 410 436 .data(int_bus_miso), 411 437 .result(mrg_bus_miso)); 412 438 413 439 lpm_mux #( 414 .lpm_size( 9),440 .lpm_size(12), 415 441 .lpm_type("LPM_MUX"), 416 442 .lpm_width(1), … … 420 446 .result(mrg_bus_busy)); 421 447 422 /*423 lpm_or #(424 .lpm_size(6),425 .lpm_type("LPM_OR"),426 .lpm_width(16)) bus_miso_or_unit (427 .data(int_bus_miso),428 .result(mrg_bus_miso));429 */430 431 448 lpm_decode #( 432 .lpm_decodes( 9),449 .lpm_decodes(12), 433 450 .lpm_type("LPM_DECODE"), 434 451 .lpm_width(4)) lpm_decode_unit ( 435 452 .data(bus_addr[31:28]), 436 .eq(bus_ssel), 437 .aclr(), 438 .clken(), 439 .clock(), 440 .enable()); 453 .eq(bus_ssel)); 454 441 455 442 456 control control_unit (
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