source: trunk/MultiChannelUSB/Paella.v@ 159

Last change on this file since 159 was 159, checked in by demin, 13 years ago

adapt to paella v2

File size: 11.2 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire I2C_SDA,
8 inout wire I2C_SCL,
9 inout wire [4:0] CON_A,
10 input wire [16:0] CON_B,
11 input wire [12:0] CON_C,
12 input wire CON_BCLK,
13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
17 input wire [2:0] ADC_D,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 localparam N = 3;
46
47 // Turn output ports off
48/*
49 assign RAM_CLK = 1'b0;
50 assign RAM_CE1 = 1'b0;
51 assign RAM_WE = 1'b0;
52 assign RAM_ADDR = 20'h00000;
53*/
54 assign RAM_CLK = sys_clock;
55 assign RAM_CE1 = 1'b0;
56
57 // Turn inout ports to tri-state
58 assign TRG = 4'bz;
59 assign CON_A = 5'bz;
60 assign USB_PA0 = 1'bz;
61 assign USB_PA1 = 1'bz;
62 assign USB_PA3 = 1'bz;
63 assign USB_PA7 = 1'bz;
64// assign RAM_DQAP = 1'bz;
65// assign RAM_DQA = 8'bz;
66// assign RAM_DQBP = 1'bz;
67// assign RAM_DQB = 8'bz;
68
69 assign USB_PA2 = ~usb_rden;
70 assign USB_PA5 = 1'b1;
71 assign USB_PA6 = ~usb_pktend;
72
73 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
74 wire usb_tx_wrreq, usb_rx_rdreq;
75 wire usb_tx_full, usb_rx_empty;
76 wire [7:0] usb_tx_data, usb_rx_data;
77
78 assign USB_SLRD = ~usb_rdreq;
79 assign USB_SLWR = ~usb_wrreq;
80
81 usb_fifo usb_unit
82 (
83 .usb_clock(USB_IFCLK),
84 .usb_data(USB_PB),
85 .usb_full(~USB_FLAGB),
86 .usb_empty(~USB_FLAGA),
87 .usb_wrreq(usb_wrreq),
88 .usb_rdreq(usb_rdreq),
89 .usb_rden(usb_rden),
90 .usb_pktend(usb_pktend),
91 .usb_addr(USB_PA4),
92
93 .clock(sys_clock),
94
95 .tx_full(usb_tx_full),
96 .tx_wrreq(usb_tx_wrreq),
97 .tx_data(usb_tx_data),
98
99 .rx_empty(usb_rx_empty),
100 .rx_rdreq(usb_rx_rdreq),
101 .rx_q(usb_rx_data)
102 );
103/*
104 reg [31:0] led_counter;
105 always @(posedge CLK_50MHz)
106 begin
107 led_counter = led_counter + 32'd1;
108 end
109 assign LED = led_counter[28];
110*/
111 wire [11:0] osc_mux_data [4:0];
112
113 wire [11:0] trg_mux_data;
114 wire trg_flag;
115
116 wire [4*12-1:0] int_mux_data [N-1:0];
117
118 wire [1:0] amp_flag [2*N-1:0];
119 wire [11:0] amp_data [2*N-1:0];
120
121 wire cnt_good [N-1:0];
122 wire [15:0] cnt_bits_wire;
123
124 wire sys_clock, sys_frame;
125
126 wire [11:0] adc_data [N-1:0];
127 wire [11:0] sys_data [N-1:0];
128 wire [11:0] tst_data;
129
130 wire [1:0] cmp_data;
131 wire [1:0] del_data;
132
133 wire [19:0] cic_data [N-1:0];
134
135 wire [11:0] dec_data [N-1:0];
136 wire [11:0] clp_data [N-1:0];
137 wire [11:0] tmp_data;
138
139
140 wire i2c_reset;
141
142 sys_pll sys_pll_unit(
143 .inclk0(CLK_50MHz),
144 .c0(sys_clock));
145
146 test test_unit(
147 .clk(ADC_FCO),
148 .data(tst_data));
149
150 adc_lvds #(
151 .size(3),
152 .width(12)) adc_lvds_unit (
153 .clock(sys_clock),
154 .lvds_dco(ADC_DCO),
155 .lvds_fco(ADC_FCO),
156 .lvds_d(ADC_D),
157 .trig(TRG[1:0]),
158 .adc_frame(sys_frame),
159 .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]}));
160
161 wire [15:0] cfg_bits [63:0];
162 wire [1023:0] int_cfg_bits;
163
164 wire [39:0] cfg_mux_selector;
165
166 wire cfg_reset;
167
168 wire [11:0] bus_ssel;
169 wire bus_wren;
170 wire [31:0] bus_addr;
171 wire [15:0] bus_mosi;
172 wire [15:0] bus_miso [10:0];
173 wire [11:0] bus_busy;
174
175 wire [15:0] mrg_bus_miso;
176 wire mrg_bus_busy;
177
178 wire [11*16-1:0] int_bus_miso;
179
180 genvar j;
181
182 generate
183 for (j = 0; j < 64; j = j + 1)
184 begin : CONFIGURATION_OUTPUT
185 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
186 end
187 endgenerate
188
189 configuration configuration_unit (
190 .clock(sys_clock),
191 .reset(cfg_reset),
192 .bus_ssel(bus_ssel[0]),
193 .bus_wren(bus_wren),
194 .bus_addr(bus_addr[4:0]),
195 .bus_mosi(bus_mosi),
196 .bus_miso(bus_miso[0]),
197 .bus_busy(bus_busy[0]),
198 .cfg_bits(int_cfg_bits));
199
200 generate
201 for (j = 0; j < 3; j = j + 1)
202 begin : MUX_DATA
203 assign int_mux_data[j] = {
204 {4'd0, amp_flag[0+2*j][0], 7'd0},
205 amp_data[0+2*j],
206 clp_data[j],
207 sys_data[j]};
208 end
209 endgenerate
210
211 assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]};
212
213 lpm_mux #(
214 .lpm_size(4*3),
215 .lpm_type("LPM_MUX"),
216 .lpm_width(12),
217 .lpm_widths(4)) trg_mux_unit (
218 .sel(cfg_bits[4][11:8]),
219 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
220 .result(trg_mux_data));
221
222 generate
223 for (j = 0; j < 5; j = j + 1)
224 begin : OSC_CHAIN
225
226 lpm_mux #(
227 .lpm_size(4*3),
228 .lpm_type("LPM_MUX"),
229 .lpm_width(12),
230 .lpm_widths(4)) osc_mux_unit (
231 .sel(cfg_mux_selector[j*8+3:j*8]),
232 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
233 .result(osc_mux_data[j]));
234
235 end
236 endgenerate
237
238 trigger trigger_unit (
239 .clock(sys_clock),
240 .frame(sys_frame),
241 .reset(cfg_bits[0][0]),
242 .cfg_data(cfg_bits[5][11:0]),
243 .trg_data(trg_mux_data),
244 .trg_flag(trg_flag));
245
246 oscilloscope oscilloscope_unit (
247 .clock(sys_clock),
248 .frame(sys_frame),
249 .reset(cfg_bits[0][1]),
250 .cfg_data(cfg_bits[5][12]),
251 .trg_flag(trg_flag),
252 .osc_data({2'd0, cmp_data, osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
253 .ram_wren(RAM_WE),
254 .ram_addr(RAM_ADDR),
255 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
256 .bus_ssel(bus_ssel[1]),
257 .bus_wren(bus_wren),
258 .bus_addr(bus_addr[19:0]),
259 .bus_mosi(bus_mosi),
260 .bus_miso(bus_miso[1]),
261 .bus_busy(bus_busy[1]));
262
263 filter #(.size(3), .width(12)) filter_unit (
264 .clock(sys_clock),
265 .frame(sys_frame),
266 .reset(1'b0),
267 .inp_data({sys_data[2], sys_data[1], sys_data[0]}),
268 .out_data({cic_data[2], cic_data[1], cic_data[0]}));
269
270
271/*
272 clip #(.shift(19), .width(19), .widthr(12)) clip_unit (
273 .clock(sys_clock),
274 .frame(sys_frame),
275 .reset(1'b0),
276 .del_data({cfg_bits[39][5:0], cfg_bits[37][5:0], cfg_bits[35+8][5:0], cfg_bits[33][5:0]}),
277 .amp_data({6'd6, 6'd6, 6'd6, 6'd6}),
278 .tau_data({cfg_bits[38], cfg_bits[36], cfg_bits[34], cfg_bits[32]}),
279 .inp_data({
280 19'd0, cic_data[2][18:0],
281 cic_data[1][18:0], cic_data[0][18:0]}),
282 .out_data({
283 tmp_data, clp_data[2],
284 clp_data[1], clp_data[0]}));
285*/
286 generate
287 for (j = 0; j < 3; j = j + 1)
288 begin : MCA_CHAIN
289
290 shift #(.shift(9), .width(19), .widthr(12)) shift_unit (
291 .clock(sys_clock),
292 .frame(sys_frame),
293 .reset(1'b0),
294 .amp_data(6'd5),
295 .inp_data(cic_data[j][18:0]),
296 .out_data(clp_data[j]));
297
298 assign sys_data[j] = (cfg_bits[1][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
299
300 amplitude #(.width(12)) amplitude_unit_1 (
301 .clock(sys_clock),
302 .frame(sys_frame),
303 .reset(1'b0),
304 .cfg_data(cfg_bits[6+2*j][11:0]),
305 .inp_data(clp_data[j]),
306 .out_flag(amp_flag[0+2*j]),
307 .out_data(amp_data[0+2*j]));
308
309 amplitude #(.width(12)) amplitude_unit_2 (
310 .clock(sys_clock),
311 .frame(sys_frame),
312 .reset(1'b0),
313 .cfg_data(cfg_bits[7+2*j][11:0]),
314 .inp_data(clp_data[j]),
315 .out_flag(amp_flag[1+2*j]),
316 .out_data(amp_data[1+2*j]));
317
318 end
319 endgenerate
320
321 histogram32 histogram32_unit (
322 .clock(sys_clock),
323 .frame(sys_frame),
324 .reset(cfg_bits[0][5]),
325 .hst_good((amp_flag[0][0]) & (cnt_good[0]) & (cfg_bits[13][1])),
326 .hst_data(amp_data[0]),
327/*
328 .hst_good((amp_flag[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
329 .hst_data(amp_data[j]),
330*/
331 .bus_ssel(bus_ssel[2]),
332 .bus_wren(bus_wren),
333 .bus_addr(bus_addr[12:0]),
334 .bus_mosi(bus_mosi),
335 .bus_miso(bus_miso[2]),
336 .bus_busy(bus_busy[2]));
337
338 counter hst_counter_unit (
339 .clock(sys_clock),
340 .frame((sys_frame) & (~amp_flag[0][1])),
341// .frame(sys_frame),
342 .reset(cfg_bits[0][8]),
343 .setup(cfg_bits[13][0]),
344 .count(cfg_bits[13][1]),
345 .bus_ssel(bus_ssel[5]),
346 .bus_wren(bus_wren),
347 .bus_addr(bus_addr[1:0]),
348 .bus_mosi(bus_mosi),
349 .bus_miso(bus_miso[5]),
350 .bus_busy(bus_busy[5]),
351 .cnt_good(cnt_good[0]));
352
353 histogram16 histogram16_unit (
354 .clock(sys_clock),
355 .frame(sys_frame),
356 .reset(cfg_bits[0][11]),
357 .hst_good((cnt_good[2]) & (~cnt_good[1])),
358 .hst_data(cnt_bits_wire),
359 .bus_ssel(bus_ssel[8]),
360 .bus_wren(bus_wren),
361 .bus_addr(bus_addr[13:0]),
362 .bus_mosi(bus_mosi),
363 .bus_miso(bus_miso[8]),
364 .bus_busy(bus_busy[8]));
365
366 counter rmt_counter_1 (
367 .clock(sys_clock),
368 .frame((sys_frame) & (~amp_flag[1][1])),
369// .frame(sys_frame),
370 .reset(cfg_bits[0][12]),
371 .setup((sys_frame) & (~cnt_good[1])),
372 .count((cnt_good[2]) & (cfg_bits[16][1])),
373 .bus_ssel(bus_ssel[9]),
374 .bus_wren(bus_wren),
375 .bus_addr(bus_addr[1:0]),
376 .bus_mosi(bus_mosi),
377 .bus_miso(bus_miso[9]),
378 .bus_busy(bus_busy[9]),
379 .cnt_good(cnt_good[1]));
380
381 counter rmt_counter_2 (
382 .clock(sys_clock),
383 .frame((sys_frame) & (~cnt_good[1])),
384 .reset(cfg_bits[0][13]),
385 .setup(cfg_bits[16][0]),
386 .count(cfg_bits[16][1]),
387 .bus_ssel(bus_ssel[10]),
388 .bus_wren(bus_wren),
389 .bus_addr(bus_addr[1:0]),
390 .bus_mosi(bus_mosi),
391 .bus_miso(bus_miso[10]),
392 .bus_busy(bus_busy[10]),
393 .cnt_good(cnt_good[2]));
394
395 lpm_counter #(
396 .lpm_direction("UP"),
397 .lpm_port_updown("PORT_UNUSED"),
398 .lpm_type("LPM_COUNTER"),
399 .lpm_width(16)) lpm_counter_component (
400 .sclr(((sys_frame) & (cnt_good[2]) & (~cnt_good[1])) | (cfg_bits[0][11])),
401 .clock(sys_clock),
402 .cnt_en((sys_frame) & (amp_flag[1][0]) & (cnt_good[1]) & (cnt_good[2]) & (cfg_bits[16][1])),
403 .q(cnt_bits_wire));
404
405 i2c_fifo i2c_unit(
406 .clock(sys_clock),
407 .reset(i2c_reset),
408/*
409 normal connection
410 .i2c_sda(I2C_SDA),
411 .i2c_scl(I2C_SCL),
412
413 following is a cross wire connection for EPT
414*/
415 .i2c_sda(I2C_SCL),
416 .i2c_scl(I2C_SDA),
417
418 .bus_ssel(bus_ssel[11]),
419 .bus_wren(bus_wren),
420 .bus_mosi(bus_mosi),
421 .bus_busy(bus_busy[11]));
422
423 generate
424 for (j = 0; j < 11; j = j + 1)
425 begin : BUS_OUTPUT
426 assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
427 end
428 endgenerate
429
430 lpm_mux #(
431 .lpm_size(11),
432 .lpm_type("LPM_MUX"),
433 .lpm_width(16),
434 .lpm_widths(4)) bus_miso_mux_unit (
435 .sel(bus_addr[31:28]),
436 .data(int_bus_miso),
437 .result(mrg_bus_miso));
438
439 lpm_mux #(
440 .lpm_size(12),
441 .lpm_type("LPM_MUX"),
442 .lpm_width(1),
443 .lpm_widths(4)) bus_busy_mux_unit (
444 .sel(bus_addr[31:28]),
445 .data(bus_busy),
446 .result(mrg_bus_busy));
447
448 lpm_decode #(
449 .lpm_decodes(12),
450 .lpm_type("LPM_DECODE"),
451 .lpm_width(4)) lpm_decode_unit (
452 .data(bus_addr[31:28]),
453 .eq(bus_ssel));
454
455
456 control control_unit (
457 .clock(sys_clock),
458 .rx_empty(usb_rx_empty),
459 .tx_full(usb_tx_full),
460 .rx_data(usb_rx_data),
461 .rx_rdreq(usb_rx_rdreq),
462 .tx_wrreq(usb_tx_wrreq),
463 .tx_data(usb_tx_data),
464 .bus_wren(bus_wren),
465 .bus_addr(bus_addr),
466 .bus_mosi(bus_mosi),
467 .bus_miso(mrg_bus_miso),
468 .bus_busy(mrg_bus_busy),
469 .led(LED));
470
471/*
472 altserial_flash_loader #(
473 .enable_shared_access("OFF"),
474 .enhanced_mode(1),
475 .intended_device_family("Cyclone III")) sfl_unit (
476 .noe(1'b0),
477 .asmi_access_granted(),
478 .asmi_access_request(),
479 .data0out(),
480 .dclkin(),
481 .scein(),
482 .sdoin());
483*/
484
485endmodule
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