1 | module oscilloscope
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2 | (
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3 | input wire clock, frame, reset,
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4 |
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5 | input wire [16:0] cfg_data,
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6 |
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7 | input wire trg_flag,
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8 |
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9 | input wire [47:0] osc_data,
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10 |
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11 | output wire ram_wren,
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12 | output wire [19:0] ram_addr,
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13 | inout wire [17:0] ram_data,
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14 |
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15 | input wire bus_ssel, bus_wren,
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16 | input wire [19:0] bus_addr,
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17 | input wire [15:0] bus_mosi,
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18 |
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19 | output wire [15:0] bus_miso,
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20 | output wire bus_busy
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21 | );
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22 |
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23 |
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24 | reg [47:0] osc_data_reg, osc_data_next;
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25 |
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26 | reg [19:0] cfg_cntr_max_reg, cfg_cntr_max_next;
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27 | reg [19:0] cfg_cntr_mid_reg, cfg_cntr_mid_next;
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28 |
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29 | reg [2:0] int_case_reg, int_case_next;
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30 |
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31 | reg int_trig_reg, int_trig_next;
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32 | reg [19:0] int_trig_addr_reg, int_trig_addr_next;
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33 | reg [19:0] int_cntr_reg, int_cntr_next;
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34 |
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35 | reg [15:0] bus_mosi_reg [2:0];
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36 | reg [15:0] bus_mosi_next [2:0];
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37 |
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38 | reg [15:0] bus_miso_reg, bus_miso_next;
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39 | reg bus_busy_reg, bus_busy_next;
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40 |
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41 | reg ram_wren_reg [2:0];
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42 | reg ram_wren_next [2:0];
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43 |
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44 | reg [17:0] ram_data_reg, ram_data_next;
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45 | reg [19:0] ram_addr_reg, ram_addr_next;
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46 |
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47 | wire [17:0] ram_wren_wire;
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48 |
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49 | assign ram_wren = ~ram_wren_reg[0];
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50 | assign ram_addr = ram_addr_reg;
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51 |
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52 | integer i;
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53 | genvar j;
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54 |
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55 | generate
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56 | for (j = 0; j < 18; j = j + 1)
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57 | begin : SRAM_WREN
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58 | assign ram_wren_wire[j] = ram_wren_reg[2];
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59 | assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[j] : 1'bz;
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60 | end
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61 | endgenerate
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62 |
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63 | always @(posedge clock)
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64 | begin
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65 | if (reset)
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66 | begin
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67 | osc_data_reg <= 48'd0;
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68 | ram_data_reg <= 18'd0;
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69 | ram_addr_reg <= 20'd0;
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70 | bus_miso_reg <= 16'd0;
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71 | bus_busy_reg <= 1'b0;
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72 | int_case_reg <= 5'd0;
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73 | int_cntr_reg <= 20'd0;
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74 | int_trig_reg <= 1'b0;
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75 | int_trig_addr_reg <= 20'd0;
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76 | cfg_cntr_max_reg <= 20'd0;
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77 | cfg_cntr_mid_reg <= 20'd0;
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78 |
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79 | for(i = 0; i <= 2; i = i + 1)
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80 | begin
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81 | ram_wren_reg[i] <= 1'b0;
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82 | bus_mosi_reg[i] <= 16'd0;
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83 | end
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84 | end
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85 | else
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86 | begin
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87 | osc_data_reg <= osc_data_next;
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88 | ram_data_reg <= ram_data_next;
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89 | ram_addr_reg <= ram_addr_next;
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90 | bus_miso_reg <= bus_miso_next;
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91 | bus_busy_reg <= bus_busy_next;
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92 | int_case_reg <= int_case_next;
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93 | int_cntr_reg <= int_cntr_next;
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94 | int_trig_reg <= int_trig_next;
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95 | int_trig_addr_reg <= int_trig_addr_next;
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96 | cfg_cntr_max_reg <= cfg_cntr_max_next;
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97 | cfg_cntr_mid_reg <= cfg_cntr_mid_next;
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98 |
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99 | for(i = 0; i <= 2; i = i + 1)
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100 | begin
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101 | ram_wren_reg[i] <= ram_wren_next[i];
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102 | bus_mosi_reg[i] <= bus_mosi_next[i];
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103 | end
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104 | end
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105 | end
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106 |
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107 |
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108 | always @*
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109 | begin
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110 |
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111 | osc_data_next = osc_data_reg;
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112 | ram_data_next = ram_data_reg;
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113 | ram_addr_next = ram_addr_reg;
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114 | bus_miso_next = bus_miso_reg;
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115 | bus_busy_next = bus_busy_reg;
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116 | int_case_next = int_case_reg;
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117 | int_cntr_next = int_cntr_reg;
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118 | int_trig_next = int_trig_reg;
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119 | int_trig_addr_next = int_trig_addr_reg;
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120 | cfg_cntr_max_next = cfg_cntr_max_reg;
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121 | cfg_cntr_mid_next = cfg_cntr_mid_reg;
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122 |
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123 | for(i = 0; i < 2; i = i + 1)
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124 | begin
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125 | ram_wren_next[i+1] = ram_wren_reg[i];
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126 | bus_mosi_next[i+1] = bus_mosi_reg[i];
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127 | end
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128 | ram_wren_next[0] = 1'b0;
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129 | bus_mosi_next[0] = 16'd0;
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130 |
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131 | case (int_case_reg)
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132 | 0:
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133 | begin
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134 | ram_data_next = 18'd0;
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135 | ram_addr_next = 20'd0;
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136 | bus_busy_next = 1'b0;
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137 | int_cntr_next = 20'd0;
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138 | int_trig_next = 1'b0;
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139 |
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140 | ram_data_next = {bus_mosi_reg[1][15:8], 1'b0, bus_mosi_reg[1][7:0], 1'b0};
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141 |
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142 | if (bus_ssel)
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143 | begin
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144 | bus_miso_next = {ram_data[17:10], ram_data[8:1]};
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145 | ram_wren_next[0] = bus_wren;
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146 | if (bus_wren)
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147 | begin
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148 | ram_addr_next = bus_addr;
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149 | bus_mosi_next[0] = bus_mosi;
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150 | end
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151 | else
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152 | begin
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153 | // ram_addr_next = int_trig_addr_reg + bus_addr;
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154 | ram_addr_next = bus_addr;
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155 | end
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156 | end
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157 | else if (cfg_data[16])
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158 | begin
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159 | // start recording
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160 | ram_wren_next[0] = 1'b1;
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161 | bus_busy_next = 1'b1;
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162 | int_case_next = 3'd1;
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163 | int_trig_addr_next = 20'd0;
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164 | cfg_cntr_max_next = {cfg_data[7:0], 10'd0};
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165 | cfg_cntr_mid_next = {cfg_data[15:8], 10'd0};
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166 | end
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167 |
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168 | end
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169 |
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170 | // sample recording
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171 | 1:
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172 | begin
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173 | ram_wren_next[0] = 1'b1;
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174 | if (frame)
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175 | begin
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176 | osc_data_next = osc_data;
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177 | ram_addr_next = ram_addr_reg + 20'd1;
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178 | int_case_next = 3'd2;
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179 |
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180 | if ((~int_trig_reg) & (trg_flag) &
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181 | (int_cntr_reg == cfg_cntr_mid_reg))
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182 | begin
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183 | int_trig_next = 1'b1;
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184 | int_trig_addr_next = ram_addr_reg;
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185 | end
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186 |
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187 | if (int_trig_reg | (int_cntr_reg < cfg_cntr_mid_reg))
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188 | begin
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189 | int_cntr_next = int_cntr_reg + 20'd1;
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190 | end
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191 | end
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192 | end
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193 |
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194 | 2:
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195 | begin
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196 | ram_wren_next[0] = 1'b1;
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197 | ram_data_next = {osc_data_reg[15:8], 1'b0, osc_data_reg[7:0], 1'b0};
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198 | ram_addr_next = ram_addr_reg + 20'd1;
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199 | int_case_next = 3'd3;
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200 | end
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201 |
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202 | 3:
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203 | begin
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204 | ram_wren_next[0] = 1'b1;
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205 | ram_data_next = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0};
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206 | ram_addr_next = ram_addr_reg + 20'd1;
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207 | int_case_next = 3'd4;
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208 | end
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209 |
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210 | 4:
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211 | begin
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212 | ram_wren_next[0] = 1'b1;
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213 | ram_data_next = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0};
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214 | int_case_next = 3'd1;
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215 | if (int_cntr_reg >= cfg_cntr_max_reg)
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216 | begin
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217 | ram_wren_next[0] = 1'b0;
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218 | ram_addr_next = 20'd0;
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219 | int_case_next = 3'd0;
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220 | end
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221 | end
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222 |
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223 | endcase
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224 | end
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225 |
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226 | assign bus_miso = bus_miso_reg;
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227 | assign bus_busy = bus_busy_reg;
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228 |
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229 | endmodule
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