Changeset 90 for trunk/MultiChannelUSB/analyser.v

Timestamp:

Feb 27, 2010, 10:10:19 PM (15 years ago)

Author:

demin

Message:

full rewrite

File:

• trunk/MultiChannelUSB/analyser.v (modified) (2 diffs)

trunk/MultiChannelUSB/analyser.v

@@ -1 +1 @@
 module analyser
         (
-                input   wire                    clk, reset,
-                input   wire                    data_ready,
+                input   wire                    clock, frame, reset,
+                input   wire    [12:0]  cfg_data,
                 input   wire    [1:0]   uwt_flag,
-                output  wire                    peak_ready
+                input   wire    [11:0]  uwt_data,
+                output  wire                    ana_good,
+                output  wire    [11:0]  ana_data,
+                output  wire    [11:0]  ana_base
         );
 
-        reg                             flag_reg, flag_next;
-        reg             [1:0]   state_reg, state_next;
+        reg                             state_reg, state_next;
         reg             [4:0]   counter_reg, counter_next;
-        reg                             peak_ready_reg;
+        reg                             good_reg, good_next;
+        reg             [11:0]  data_reg, data_next;
 
+        reg             [19:0]  buffer_reg [31:0];
+        reg             [19:0]  buffer_next [31:0];
+
+        wire    [19:0]  sample = {8'd0, uwt_data};
+        wire    [11:0]  baseline = buffer_reg[31][16:5];
         wire                    counter_max = (&counter_reg);
-        wire                    peak_ready_int = (flag_reg & data_ready & uwt_flag[0] & counter_max);
 
-        always @(posedge clk)
+        integer i;
+
+        always @(posedge clock)
         begin
                 if (reset)
                 begin
-                        flag_reg <= 1'b0;
-                        state_reg <= 2'd0;
+                        state_reg <= 1'b0;
                         counter_reg <= 5'd0;
+                        good_reg <= 1'b0;
+                        data_reg <= 12'd0;
+                        for(i = 0; i <= 31; i = i + 1)
+                        begin
+                                buffer_reg[i] <= 20'hfffff;
+                        end
                 end
                 else
                 begin
-                        flag_reg <= flag_next;
                         state_reg <= state_next;
                         counter_reg <= counter_next;
+                        good_reg <= good_next;
+                        data_reg <= data_next;
+
+                        for(i = 0; i <= 31; i = i + 1)
+                        begin
+                                buffer_reg[i] <= buffer_next[i];
+                        end
                 end
         end
@@ -33 +53 @@
         always @*
         begin
-                flag_next = flag_reg;
                 state_next = state_reg;
                 counter_next = counter_reg;
+                good_next = good_reg;
+                data_next = data_reg;
+                
+                for(i = 0; i <= 31; i = i + 1)
+                begin
+                        buffer_next[i] = buffer_reg[i];
+                end
+
                 case (state_reg)
-                        0: // skip first 16 samples
+                        0: // skip first 32 samples
                         begin
-                                flag_next = 1'b0;
-                                if (data_ready)
+                                if (frame)
                                 begin
                                         counter_next = counter_reg + 5'd1;
                                         if (counter_max)
                                         begin
-                                                state_next = 2'd1;
+                                                state_next = 1'b1;
                                         end
                 end
                         end
 
-                        1: // skip first 16 minima
+                        1:
                         begin
-                                flag_next = 1'b0;
-                                if (data_ready & uwt_flag[1])
+                                if (frame)
                                 begin
-                                        counter_next = counter_reg + 5'd1;
+
+                                        if (cfg_data[12])
+                                        begin
+                                                if (uwt_data > baseline)
+                                                begin
+                                                        data_next = uwt_data - baseline;
+                                                end
+                                                else
+                                                begin
+                                                        data_next = 12'd0;
+                                                end
+                                        end
+                                        else
+                                        begin
+                                                if (uwt_data > cfg_data[11:0])
+                                                begin
+                                                        data_next = uwt_data - cfg_data[11:0];
+                                                end
+                                                else
+                                                begin
+                                                        data_next = 12'd0;
+                                                end
+                                        end
+
+        
+                                        for(i = 0; i < 31; i = i + 1)
+                                        begin
+                                                buffer_next[i+1] = buffer_reg[i] + sample;
+                                        end
+                                        buffer_next[0] = sample;
+        
+                                        good_next = uwt_flag[0] & counter_max;
+
+                                        // skip first 32 baseline samples
+                                        // skip 32 samples after peak
                                         if (counter_max)
                                         begin
-                                                state_next = 2'd2;
+                                                if (uwt_flag[0])
+                                                begin
+                                                        counter_next = 5'd0;
+                                                end
                                         end
-                end
-                        end
-
-                        2:
-                        begin
-                                flag_next = 1'b1;
-                                if (data_ready)
-                                begin
-                                        if (~counter_max)
+                                        else
                                         begin
                                                 counter_next = counter_reg + 5'd1;
                                         end
-                                        if (peak_ready_int)
-                                        begin
-                                                counter_next = 5'd0;
-                                        end
-                end
-                        end
-
-                        default:
-                        begin
-                                flag_next = 1'b0;
-                                state_next = 2'd0;
-                                counter_next = 5'd0;
+                                end
                         end
                 endcase
         end
 
-        assign  peak_ready = peak_ready_int;
+        assign ana_good = good_reg;
+        assign ana_data = data_reg;
+        assign ana_base = baseline;
 
 endmodule