Changeset 90 for trunk/MultiChannelUSB/histogram.v
- Timestamp:
- Feb 27, 2010, 10:10:19 PM (15 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/histogram.v (modified) (9 diffs)
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trunk/MultiChannelUSB/histogram.v
r88 r90 1 1 module histogram 2 #(3 parameter W = 32 // bin resolution4 )5 2 ( 6 input wire clk, reset, 7 input wire data_ready, 8 input wire [11:0] data, address, 9 output wire [W-1:0] q 3 input wire clock, frame, reset, 4 5 input wire [40:0] cfg_data, 6 7 input wire hst_good, 8 input wire [11:0] hst_data, 9 10 input wire bus_ssel, bus_wren, 11 input wire [12:0] bus_addr, 12 input wire [15:0] bus_mosi, 13 14 output wire [15:0] bus_miso, 15 output wire bus_busy 10 16 ); 11 17 12 18 // signal declaration 13 reg [3:0] state_reg, state_next; 14 reg wren_reg, wren_next; 15 reg [11:0] addr_reg, addr_next; 16 reg [W-1:0] data_reg, data_next; 17 18 wire [W-1:0] q_a_wire, q_b_wire; 19 reg [3:0] int_case_reg, int_case_next; 20 reg int_wren_reg, int_wren_next; 21 reg [11:0] int_addr_reg, int_addr_next; 22 reg [31:0] int_data_reg, int_data_next; 23 24 reg [12:0] bus_addr_reg, bus_addr_next; 25 reg [15:0] bus_miso_reg, bus_miso_next; 26 27 reg bus_wren_reg, bus_wren_next; 28 reg [15:0] bus_mosi_reg, bus_mosi_next; 29 30 wire [31:0] q_a_wire; 31 wire [15:0] q_b_wire; 19 32 20 33 altsyncram #( … … 28 41 .lpm_type("altsyncram"), 29 42 .numwords_a(4096), 30 .numwords_b( 4096),43 .numwords_b(8192), 31 44 .operation_mode("BIDIR_DUAL_PORT"), 32 45 .outdata_aclr_a("NONE"), … … 36 49 .power_up_uninitialized("FALSE"), 37 50 .read_during_write_mode_mixed_ports("OLD_DATA"), 51 .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"), 52 .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"), 38 53 .widthad_a(12), 39 .widthad_b(1 2),40 .width_a( W),41 .width_b( W),54 .widthad_b(13), 55 .width_a(32), 56 .width_b(16), 42 57 .width_byteena_a(1), 43 58 .width_byteena_b(1), 44 59 .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit( 45 .wren_a( wren_reg),46 .clock0(cl k),47 .wren_b( 1'b0),48 .address_a( addr_reg),49 .address_b( address),50 .data_a( data_reg),51 .data_b( ),60 .wren_a(int_wren_reg), 61 .clock0(clock), 62 .wren_b(bus_wren_reg), 63 .address_a(int_addr_reg), 64 .address_b(bus_addr_reg), 65 .data_a(int_data_reg), 66 .data_b(bus_mosi_reg), 52 67 .q_a(q_a_wire), 53 68 .q_b(q_b_wire), … … 68 83 69 84 // body 70 always @(posedge cl k)85 always @(posedge clock) 71 86 begin 72 87 if (reset) 73 88 begin 74 wren_reg <= 1'b1; 75 addr_reg <= 12'd0; 76 data_reg <= 32'd0; 77 state_reg <= 4'b1; 89 int_wren_reg <= 1'b1; 90 int_addr_reg <= 12'd0; 91 int_data_reg <= 32'd0; 92 int_case_reg <= 4'b1; 93 bus_addr_reg <= 13'd0; 94 bus_miso_reg <= 16'd0; 95 bus_wren_reg <= 1'b0; 96 bus_mosi_reg <= 16'd0; 78 97 end 79 98 else 80 99 begin 81 wren_reg <= wren_next; 82 addr_reg <= addr_next; 83 data_reg <= data_next; 84 state_reg <= state_next; 100 int_wren_reg <= int_wren_next; 101 int_addr_reg <= int_addr_next; 102 int_data_reg <= int_data_next; 103 int_case_reg <= int_case_next; 104 bus_addr_reg <= bus_addr_next; 105 bus_miso_reg <= bus_miso_next; 106 bus_wren_reg <= bus_wren_next; 107 bus_mosi_reg <= bus_mosi_next; 108 end 109 end 110 111 always @* 112 begin 113 bus_addr_next = bus_addr_reg; 114 bus_miso_next = bus_miso_reg; 115 116 bus_wren_next = 1'b0; 117 bus_mosi_next = bus_mosi_reg; 118 119 if (bus_ssel) 120 begin 121 bus_miso_next = q_b_wire; 122 bus_addr_next = bus_addr; 123 bus_wren_next = bus_wren; 124 if (bus_wren) 125 begin 126 bus_mosi_next = bus_mosi; 127 end 85 128 end 86 129 end … … 88 131 always @* 89 132 begin 90 wren_next = wren_reg; 91 addr_next = addr_reg; 92 data_next = data_reg; 93 state_next = state_reg; 94 case (state_reg) 133 int_wren_next = int_wren_reg; 134 int_addr_next = int_addr_reg; 135 int_data_next = int_data_reg; 136 int_case_next = int_case_reg; 137 138 case (int_case_reg) 95 139 0: 96 140 begin 97 // nothing to do 98 wren_next = 1'b0; 99 addr_next = 12'd0; 100 data_next = 32'd0; 101 state_next = 4'd0; 141 int_wren_next = 1'b0; 142 int_addr_next = 12'd0; 143 int_data_next = 32'd0; 102 144 end 103 145 … … 105 147 begin 106 148 // write zeros 107 if (& addr_reg)108 begin 109 wren_next = 1'b0;110 state_next = 4'd2;149 if (&int_addr_reg) 150 begin 151 int_wren_next = 1'b0; 152 int_case_next = 4'd2; 111 153 end 112 154 else 113 155 begin 114 addr_next =addr_reg + 12'd1;156 int_addr_next = int_addr_reg + 12'd1; 115 157 end 116 158 end … … 118 160 2: 119 161 begin 120 wren_next = 1'b0; 121 if (data_ready) 122 begin 123 addr_next = data; 124 state_next = 4'd3; 162 int_wren_next = 1'b0; 163 if (&int_data_reg) 164 begin 165 int_case_next = 4'd0; 166 end 167 else if (frame & hst_good) 168 begin 169 int_addr_next = hst_data; 170 int_case_next = 4'd3; 125 171 end 126 172 end … … 128 174 3: 129 175 begin 130 state_next = 4'd4;176 int_case_next = 4'd4; 131 177 end 132 178 133 179 4: 134 180 begin 135 state_next = 5'd4;181 int_case_next = 4'd5; 136 182 end 137 183 138 184 5: 139 185 begin 140 if (&q_a_wire) 141 begin 142 state_next = 4'd0; 143 end 144 else 145 begin 146 wren_next = 1'b1; 147 data_next = q_a_wire + 32'd1; 148 state_next = 4'd2; 149 end 186 int_wren_next = 1'b1; 187 int_data_next = q_a_wire + 32'd1; 188 int_case_next = 4'd2; 150 189 end 151 190 152 191 default: 153 192 begin 154 wren_next = 1'b0;155 addr_next = 12'd0;156 data_next = 32'd0;157 state_next = 4'd0;193 int_wren_next = 1'b0; 194 int_addr_next = 12'd0; 195 int_data_next = 32'd0; 196 int_case_next = 4'd0; 158 197 end 159 198 endcase … … 161 200 162 201 // output logic 163 assign q = q_b_wire; 202 assign bus_miso = bus_miso_reg; 203 assign bus_busy = 1'b0; 164 204 endmodule
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