Ignore:
Timestamp:
Dec 21, 2009, 5:09:06 PM (15 years ago)
Author:
demin
Message:

improve timings in all components

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/MultiChannelUSB/Paella.qsf

    r72 r84  
    5959set_global_assignment -name VERILOG_FILE histogram.v
    6060set_global_assignment -name VERILOG_FILE trigger.v
     61set_global_assignment -name VERILOG_FILE suppression.v
    6162set_global_assignment -name VERILOG_FILE oscilloscope.v
    6263set_global_assignment -name VERILOG_FILE usb_fifo.v
     
    6566set_global_assignment -name VERILOG_FILE test.v
    6667set_global_assignment -name VERILOG_FILE test_pll.v
     68set_global_assignment -name VERILOG_FILE sys_pll.v
    6769set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
    6870set_global_assignment -name ENABLE_CLOCK_LATENCY ON
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