Changeset 84 for trunk/MultiChannelUSB/analyser.v

Timestamp:

Dec 21, 2009, 5:09:06 PM (15 years ago)

Author:

demin

Message:

improve timings in all components

File:

• trunk/MultiChannelUSB/analyser.v (modified) (5 diffs)

trunk/MultiChannelUSB/analyser.v

@@ -4 +4 @@
                 input   wire                    data_ready,
                 input   wire    [1:0]   uwt_flag,
-                output  wire                    peak_ready
+                output  wire                    peak_ready,
+                output  wire                    peak_debug
         );
 
+        reg                             flag_reg, flag_next;
         reg             [1:0]   state_reg, state_next;
-        reg             [3:0]   counter_reg, counter_next;
-        reg                             peak_ready_reg, peak_ready_next;
+        reg             [4:0]   counter_reg, counter_next;
+        reg                             peak_ready_reg;
 
         wire                    counter_max = (&counter_reg);
+        wire                    peak_ready_int = (flag_reg & data_ready & uwt_flag[0] & counter_max);
 
         always @(posedge clk)
@@ -17 +20 @@
                 if (reset)
                 begin
+                        flag_reg <= 1'b0;
                         state_reg <= 2'd0;
-                        counter_reg <= 4'd0;
+                        counter_reg <= 5'd0;
                         peak_ready_reg <= 1'b0;
                 end
                 else
                 begin
+                        flag_reg <= flag_next;
                         state_reg <= state_next;
                         counter_reg <= counter_next;
-                        peak_ready_reg <= peak_ready_next;
+                        peak_ready_reg <= peak_ready_int;
                 end
         end
@@ -31 +36 @@
         always @*
         begin
+                flag_next = flag_reg;
                 state_next = state_reg;
                 counter_next = counter_reg;
-                peak_ready_next = peak_ready_reg;
                 case (state_reg)
                         0: // skip first 16 samples
                         begin
-                                peak_ready_next = 1'b0;
+                                flag_next = 1'b0;
                                 if (data_ready)
                                 begin
-                                        counter_next = counter_reg + 4'd1;
+                                        counter_next = counter_reg + 5'd1;
                                         if (counter_max)
                                         begin
@@ -50 +55 @@
                         1: // skip first 16 minima
                         begin
+                                flag_next = 1'b0;
                                 if (data_ready & uwt_flag[1])
                                 begin
-                                        counter_next = counter_reg + 4'd1;
+                                        counter_next = counter_reg + 5'd1;
                                         if (counter_max)
                                         begin
@@ -62 +68 @@
                         2:
                         begin
-                                if (data_ready & uwt_flag[0] & counter_max)
+                                flag_next = 1'b1;
+                                if (data_ready)
                                 begin
-                                        counter_next = 4'd0;
-                                        peak_ready_next = 1'b1;
-                end
-                else
-                begin
                                         if (~counter_max)
                                         begin
-                                                counter_next = counter_reg + 4'd1;
+                                                counter_next = counter_reg + 5'd1;
                                         end
-                                        peak_ready_next = 1'b0;
-                                end
+                                        if (peak_ready_int)
+                                        begin
+                                                counter_next = 5'd0;
+                                        end
+                end
                         end
 
                         default:
                         begin
+                                flag_next = 1'b0;
                                 state_next = 2'd0;
-                                counter_next = 4'd0;
-                                peak_ready_next = 1'b0;
+                                counter_next = 5'd0;
                         end
                 endcase
         end
 
-        assign  peak_ready = peak_ready_reg;
+        assign  peak_ready = peak_ready_int;
+        assign  peak_debug = peak_ready_reg;
 endmodule