source: trunk/MultiChannelUSB/Paella.v@ 167

Last change on this file since 167 was 166, checked in by demin, 13 years ago

fix histogram connections
File size: 13.2 KB
RevLine 
[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
[68]7 inout wire I2C_SDA,
[72]8 inout wire I2C_SCL,
[68]9 inout wire [4:0] CON_A,
[159]10 input wire [16:0] CON_B,
[63]11 input wire [12:0] CON_C,
[159]12 input wire CON_BCLK,
[27]13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
[41]17 input wire [2:0] ADC_D,
[27]18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
[30]25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
[27]33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
[72]45 localparam N = 3;
46
[27]47 // Turn output ports off
[65]48/*
[27]49 assign RAM_CLK = 1'b0;
50 assign RAM_CE1 = 1'b0;
51 assign RAM_WE = 1'b0;
52 assign RAM_ADDR = 20'h00000;
[65]53*/
[90]54 assign RAM_CLK = sys_clock;
[65]55 assign RAM_CE1 = 1'b0;
[27]56
57 // Turn inout ports to tri-state
58 assign TRG = 4'bz;
[68]59 assign CON_A = 5'bz;
[30]60 assign USB_PA0 = 1'bz;
61 assign USB_PA1 = 1'bz;
62 assign USB_PA3 = 1'bz;
63 assign USB_PA7 = 1'bz;
[65]64// assign RAM_DQAP = 1'bz;
65// assign RAM_DQA = 8'bz;
66// assign RAM_DQBP = 1'bz;
67// assign RAM_DQB = 8'bz;
[27]68
[30]69 assign USB_PA2 = ~usb_rden;
[159]70 assign USB_PA5 = 1'b1;
[30]71 assign USB_PA6 = ~usb_pktend;
72
[27]73 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[59]74 wire usb_tx_wrreq, usb_rx_rdreq;
75 wire usb_tx_full, usb_rx_empty;
76 wire [7:0] usb_tx_data, usb_rx_data;
[27]77
78 assign USB_SLRD = ~usb_rdreq;
79 assign USB_SLWR = ~usb_wrreq;
80
[59]81 usb_fifo usb_unit
[27]82 (
[159]83 .usb_clock(USB_IFCLK),
[27]84 .usb_data(USB_PB),
85 .usb_full(~USB_FLAGB),
86 .usb_empty(~USB_FLAGA),
87 .usb_wrreq(usb_wrreq),
88 .usb_rdreq(usb_rdreq),
89 .usb_rden(usb_rden),
90 .usb_pktend(usb_pktend),
[159]91 .usb_addr(USB_PA4),
[34]92
[159]93 .clock(sys_clock),
[34]94
[59]95 .tx_full(usb_tx_full),
96 .tx_wrreq(usb_tx_wrreq),
97 .tx_data(usb_tx_data),
[34]98
[59]99 .rx_empty(usb_rx_empty),
100 .rx_rdreq(usb_rx_rdreq),
101 .rx_q(usb_rx_data)
[27]102 );
[159]103/*
104 reg [31:0] led_counter;
105 always @(posedge CLK_50MHz)
106 begin
107 led_counter = led_counter + 32'd1;
108 end
109 assign LED = led_counter[28];
110*/
111 wire [11:0] osc_mux_data [4:0];
[44]112
[90]113 wire [11:0] trg_mux_data;
114 wire trg_flag;
[72]115
[159]116 wire [4*12-1:0] int_mux_data [N-1:0];
[72]117
[162]118 wire [1:0] amp_flag [3*N-1:0];
119 wire [11:0] amp_data [3*N-1:0];
[159]120
[162]121 wire [1:0] amp_mux_flag [2:0];
122 wire [11:0] amp_mux_data [2:0];
[161]123
[162]124 wire cnt_good [3:0];
[159]125 wire [15:0] cnt_bits_wire;
126
[90]127 wire sys_clock, sys_frame;
[72]128
[159]129 wire [11:0] adc_data [N-1:0];
[101]130 wire [11:0] sys_data [N-1:0];
[159]131 wire [11:0] tst_data;
[84]132
[159]133 wire [1:0] cmp_data;
134 wire [1:0] del_data;
[63]135
[159]136 wire [19:0] cic_data [N-1:0];
[63]137
[159]138 wire [11:0] dec_data [N-1:0];
139 wire [11:0] clp_data [N-1:0];
140 wire [11:0] tmp_data;
[54]141
[48]142
[159]143 wire i2c_reset;
144
[101]145 sys_pll sys_pll_unit(
146 .inclk0(CLK_50MHz),
147 .c0(sys_clock));
148
[59]149 test test_unit(
[84]150 .clk(ADC_FCO),
[159]151 .data(tst_data));
[48]152
[63]153 adc_lvds #(
[81]154 .size(3),
[63]155 .width(12)) adc_lvds_unit (
[159]156 .clock(sys_clock),
[41]157 .lvds_dco(ADC_DCO),
158 .lvds_fco(ADC_FCO),
[159]159 .lvds_d(ADC_D),
160 .trig(TRG[1:0]),
161 .adc_frame(sys_frame),
162 .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]}));
[101]163
[159]164 wire [15:0] cfg_bits [63:0];
165 wire [1023:0] int_cfg_bits;
[72]166
[159]167 wire [39:0] cfg_mux_selector;
[72]168
169 wire cfg_reset;
170
[159]171 wire [11:0] bus_ssel;
[90]172 wire bus_wren;
173 wire [31:0] bus_addr;
174 wire [15:0] bus_mosi;
[159]175 wire [15:0] bus_miso [10:0];
176 wire [11:0] bus_busy;
[72]177
[90]178 wire [15:0] mrg_bus_miso;
179 wire mrg_bus_busy;
[72]180
[159]181 wire [11*16-1:0] int_bus_miso;
[84]182
[90]183 genvar j;
[72]184
[44]185 generate
[159]186 for (j = 0; j < 64; j = j + 1)
[90]187 begin : CONFIGURATION_OUTPUT
188 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
189 end
190 endgenerate
[72]191
[90]192 configuration configuration_unit (
193 .clock(sys_clock),
194 .reset(cfg_reset),
195 .bus_ssel(bus_ssel[0]),
196 .bus_wren(bus_wren),
[101]197 .bus_addr(bus_addr[4:0]),
[90]198 .bus_mosi(bus_mosi),
199 .bus_miso(bus_miso[0]),
200 .bus_busy(bus_busy[0]),
201 .cfg_bits(int_cfg_bits));
[72]202
[90]203 generate
204 for (j = 0; j < 3; j = j + 1)
205 begin : MUX_DATA
206 assign int_mux_data[j] = {
[166]207 {4'd0, amp_flag[0+j][0], 7'd0},
208 amp_data[0+j],
[159]209 clp_data[j],
[101]210 sys_data[j]};
[90]211 end
212 endgenerate
[72]213
[159]214 assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]};
[75]215
[90]216 lpm_mux #(
[159]217 .lpm_size(4*3),
[90]218 .lpm_type("LPM_MUX"),
219 .lpm_width(12),
[159]220 .lpm_widths(4)) trg_mux_unit (
221 .sel(cfg_bits[4][11:8]),
[90]222 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
223 .result(trg_mux_data));
[72]224
[161]225 lpm_mux #(
226 .lpm_size(3),
227 .lpm_type("LPM_MUX"),
228 .lpm_width(14),
229 .lpm_widths(2)) amp_mux_unit_1 (
[162]230 .sel(cfg_bits[6][1:0]),
[161]231 .data({
232 {amp_flag[2], amp_data[2]},
[162]233 {amp_flag[1], amp_data[1]},
[161]234 {amp_flag[0], amp_data[0]}}),
235 .result({amp_mux_flag[0], amp_mux_data[0]}));
236
237 lpm_mux #(
238 .lpm_size(3),
239 .lpm_type("LPM_MUX"),
240 .lpm_width(14),
241 .lpm_widths(2)) amp_mux_unit_2 (
[162]242 .sel(cfg_bits[6][5:4]),
[161]243 .data({
244 {amp_flag[5], amp_data[5]},
[162]245 {amp_flag[4], amp_data[4]},
246 {amp_flag[3], amp_data[3]}}),
[161]247 .result({amp_mux_flag[1], amp_mux_data[1]}));
248
[162]249 lpm_mux #(
250 .lpm_size(3),
251 .lpm_type("LPM_MUX"),
252 .lpm_width(14),
253 .lpm_widths(2)) amp_mux_unit_3 (
254 .sel(cfg_bits[6][9:8]),
255 .data({
256 {amp_flag[8], amp_data[8]},
257 {amp_flag[7], amp_data[7]},
258 {amp_flag[6], amp_data[6]}}),
259 .result({amp_mux_flag[2], amp_mux_data[2]}));
260
[90]261 generate
[159]262 for (j = 0; j < 5; j = j + 1)
[90]263 begin : OSC_CHAIN
[72]264
265 lpm_mux #(
[159]266 .lpm_size(4*3),
[72]267 .lpm_type("LPM_MUX"),
268 .lpm_width(12),
[159]269 .lpm_widths(4)) osc_mux_unit (
270 .sel(cfg_mux_selector[j*8+3:j*8]),
[90]271 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
272 .result(osc_mux_data[j]));
273
274 end
275 endgenerate
[72]276
[90]277 trigger trigger_unit (
278 .clock(sys_clock),
279 .frame(sys_frame),
[101]280 .reset(cfg_bits[0][0]),
281 .cfg_data(cfg_bits[5][11:0]),
[90]282 .trg_data(trg_mux_data),
283 .trg_flag(trg_flag));
[27]284
[90]285 oscilloscope oscilloscope_unit (
286 .clock(sys_clock),
287 .frame(sys_frame),
[101]288 .reset(cfg_bits[0][1]),
[159]289 .cfg_data(cfg_bits[5][12]),
[90]290 .trg_flag(trg_flag),
[159]291 .osc_data({2'd0, cmp_data, osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
[90]292 .ram_wren(RAM_WE),
293 .ram_addr(RAM_ADDR),
294 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
295 .bus_ssel(bus_ssel[1]),
296 .bus_wren(bus_wren),
297 .bus_addr(bus_addr[19:0]),
298 .bus_mosi(bus_mosi),
299 .bus_miso(bus_miso[1]),
300 .bus_busy(bus_busy[1]));
[72]301
[159]302 filter #(.size(3), .width(12)) filter_unit (
303 .clock(sys_clock),
304 .frame(sys_frame),
305 .reset(1'b0),
306 .inp_data({sys_data[2], sys_data[1], sys_data[0]}),
307 .out_data({cic_data[2], cic_data[1], cic_data[0]}));
308
[101]309
[159]310/*
311 clip #(.shift(19), .width(19), .widthr(12)) clip_unit (
312 .clock(sys_clock),
313 .frame(sys_frame),
314 .reset(1'b0),
315 .del_data({cfg_bits[39][5:0], cfg_bits[37][5:0], cfg_bits[35+8][5:0], cfg_bits[33][5:0]}),
316 .amp_data({6'd6, 6'd6, 6'd6, 6'd6}),
317 .tau_data({cfg_bits[38], cfg_bits[36], cfg_bits[34], cfg_bits[32]}),
318 .inp_data({
319 19'd0, cic_data[2][18:0],
320 cic_data[1][18:0], cic_data[0][18:0]}),
321 .out_data({
322 tmp_data, clp_data[2],
323 clp_data[1], clp_data[0]}));
324*/
[90]325 generate
326 for (j = 0; j < 3; j = j + 1)
327 begin : MCA_CHAIN
[159]328
329 shift #(.shift(9), .width(19), .widthr(12)) shift_unit (
[90]330 .clock(sys_clock),
331 .frame(sys_frame),
332 .reset(1'b0),
[159]333 .amp_data(6'd5),
334 .inp_data(cic_data[j][18:0]),
335 .out_data(clp_data[j]));
336
337 assign sys_data[j] = (cfg_bits[1][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
338
339 amplitude #(.width(12)) amplitude_unit_1 (
[90]340 .clock(sys_clock),
341 .frame(sys_frame),
342 .reset(1'b0),
[162]343 .cfg_data(cfg_bits[7][11:0]),
[161]344// .cfg_data(cfg_bits[6+2*j][11:0]),
[159]345 .inp_data(clp_data[j]),
[162]346 .out_flag(amp_flag[0+j]),
347 .out_data(amp_data[0+j]));
[159]348
349 amplitude #(.width(12)) amplitude_unit_2 (
[90]350 .clock(sys_clock),
351 .frame(sys_frame),
352 .reset(1'b0),
[162]353 .cfg_data(cfg_bits[8][11:0]),
[161]354// .cfg_data(cfg_bits[7+2*j][11:0]),
[159]355 .inp_data(clp_data[j]),
[162]356 .out_flag(amp_flag[3+j]),
357 .out_data(amp_data[3+j]));
[54]358
[162]359 amplitude #(.width(12)) amplitude_unit_3 (
360 .clock(sys_clock),
361 .frame(sys_frame),
362 .reset(1'b0),
363 .cfg_data(cfg_bits[9][11:0]),
364// .cfg_data(cfg_bits[7+2*j][11:0]),
365 .inp_data(clp_data[j]),
366 .out_flag(amp_flag[6+j]),
367 .out_data(amp_data[6+j]));
368
[44]369 end
370 endgenerate
[27]371
[162]372 histogram32 histogram32_unit_1 (
[159]373 .clock(sys_clock),
374 .frame(sys_frame),
375 .reset(cfg_bits[0][5]),
[161]376 .hst_good((amp_mux_flag[0][0]) & (cnt_good[0]) & (cfg_bits[13][1])),
377 .hst_data(amp_mux_data[0]),
[159]378 .bus_ssel(bus_ssel[2]),
379 .bus_wren(bus_wren),
380 .bus_addr(bus_addr[12:0]),
381 .bus_mosi(bus_mosi),
382 .bus_miso(bus_miso[2]),
383 .bus_busy(bus_busy[2]));
384
[162]385 counter hst_counter_unit_1 (
[159]386 .clock(sys_clock),
[161]387 .frame((sys_frame) & (~amp_mux_flag[0][1])),
[159]388// .frame(sys_frame),
389 .reset(cfg_bits[0][8]),
390 .setup(cfg_bits[13][0]),
391 .count(cfg_bits[13][1]),
392 .bus_ssel(bus_ssel[5]),
393 .bus_wren(bus_wren),
394 .bus_addr(bus_addr[1:0]),
395 .bus_mosi(bus_mosi),
396 .bus_miso(bus_miso[5]),
397 .bus_busy(bus_busy[5]),
398 .cnt_good(cnt_good[0]));
399
[162]400 histogram32 histogram32_unit_2 (
401 .clock(sys_clock),
402 .frame(sys_frame),
[166]403 .reset(cfg_bits[0][6]),
404 .hst_good((amp_mux_flag[1][0]) & (cnt_good[1]) & (cfg_bits[14][1])),
405 .hst_data(amp_mux_data[1]),
[162]406 .bus_ssel(bus_ssel[3]),
407 .bus_wren(bus_wren),
408 .bus_addr(bus_addr[12:0]),
409 .bus_mosi(bus_mosi),
410 .bus_miso(bus_miso[3]),
411 .bus_busy(bus_busy[3]));
412
413 counter hst_counter_unit_2 (
414 .clock(sys_clock),
[166]415 .frame((sys_frame) & (~amp_mux_flag[1][1])),
[162]416// .frame(sys_frame),
417 .reset(cfg_bits[0][8]),
418 .setup(cfg_bits[14][0]),
419 .count(cfg_bits[14][1]),
420 .bus_ssel(bus_ssel[6]),
421 .bus_wren(bus_wren),
422 .bus_addr(bus_addr[1:0]),
423 .bus_mosi(bus_mosi),
424 .bus_miso(bus_miso[6]),
425 .bus_busy(bus_busy[6]),
426 .cnt_good(cnt_good[1]));
427
[159]428 histogram16 histogram16_unit (
429 .clock(sys_clock),
430 .frame(sys_frame),
431 .reset(cfg_bits[0][11]),
[162]432 .hst_good((cnt_good[3]) & (~cnt_good[2])),
[166]433 .hst_data(cnt_bits_wire < 16'd9999 ? cnt_bits_wire[13:0] : 14'd9999),
[159]434 .bus_ssel(bus_ssel[8]),
435 .bus_wren(bus_wren),
436 .bus_addr(bus_addr[13:0]),
437 .bus_mosi(bus_mosi),
438 .bus_miso(bus_miso[8]),
439 .bus_busy(bus_busy[8]));
440
441 counter rmt_counter_1 (
442 .clock(sys_clock),
[166]443 .frame((sys_frame) & (~amp_mux_flag[2][1])),
[159]444// .frame(sys_frame),
445 .reset(cfg_bits[0][12]),
[162]446 .setup((sys_frame) & (~cnt_good[2])),
447 .count((cnt_good[3]) & (cfg_bits[16][1])),
[159]448 .bus_ssel(bus_ssel[9]),
449 .bus_wren(bus_wren),
450 .bus_addr(bus_addr[1:0]),
451 .bus_mosi(bus_mosi),
452 .bus_miso(bus_miso[9]),
453 .bus_busy(bus_busy[9]),
[162]454 .cnt_good(cnt_good[2]));
[159]455
456 counter rmt_counter_2 (
457 .clock(sys_clock),
[162]458 .frame((sys_frame) & (~cnt_good[2])),
[159]459 .reset(cfg_bits[0][13]),
460 .setup(cfg_bits[16][0]),
461 .count(cfg_bits[16][1]),
462 .bus_ssel(bus_ssel[10]),
463 .bus_wren(bus_wren),
464 .bus_addr(bus_addr[1:0]),
465 .bus_mosi(bus_mosi),
466 .bus_miso(bus_miso[10]),
467 .bus_busy(bus_busy[10]),
[162]468 .cnt_good(cnt_good[3]));
[159]469
470 lpm_counter #(
471 .lpm_direction("UP"),
472 .lpm_port_updown("PORT_UNUSED"),
473 .lpm_type("LPM_COUNTER"),
474 .lpm_width(16)) lpm_counter_component (
[162]475 .sclr(((sys_frame) & (cnt_good[3]) & (~cnt_good[2])) | (cfg_bits[0][11])),
[159]476 .clock(sys_clock),
[166]477 .cnt_en((sys_frame) & (amp_mux_flag[2][0]) & (cnt_good[2]) & (cnt_good[3]) & (cfg_bits[16][1])),
[159]478 .q(cnt_bits_wire));
479
[68]480 i2c_fifo i2c_unit(
[90]481 .clock(sys_clock),
482 .reset(i2c_reset),
[70]483/*
484 normal connection
[68]485 .i2c_sda(I2C_SDA),
[70]486 .i2c_scl(I2C_SCL),
[68]487
[70]488 following is a cross wire connection for EPT
489*/
490 .i2c_sda(I2C_SCL),
[90]491 .i2c_scl(I2C_SDA),
492
[159]493 .bus_ssel(bus_ssel[11]),
[90]494 .bus_wren(bus_wren),
495 .bus_mosi(bus_mosi),
[159]496 .bus_busy(bus_busy[11]));
[70]497
[90]498 generate
[159]499 for (j = 0; j < 11; j = j + 1)
[90]500 begin : BUS_OUTPUT
501 assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
502 end
503 endgenerate
504
505 lpm_mux #(
[159]506 .lpm_size(11),
[90]507 .lpm_type("LPM_MUX"),
508 .lpm_width(16),
[159]509 .lpm_widths(4)) bus_miso_mux_unit (
510 .sel(bus_addr[31:28]),
[90]511 .data(int_bus_miso),
512 .result(mrg_bus_miso));
513
514 lpm_mux #(
[159]515 .lpm_size(12),
[90]516 .lpm_type("LPM_MUX"),
517 .lpm_width(1),
[101]518 .lpm_widths(4)) bus_busy_mux_unit (
519 .sel(bus_addr[31:28]),
[90]520 .data(bus_busy),
521 .result(mrg_bus_busy));
522
523 lpm_decode #(
[159]524 .lpm_decodes(12),
[90]525 .lpm_type("LPM_DECODE"),
[101]526 .lpm_width(4)) lpm_decode_unit (
527 .data(bus_addr[31:28]),
[159]528 .eq(bus_ssel));
[90]529
[159]530
[59]531 control control_unit (
[90]532 .clock(sys_clock),
[59]533 .rx_empty(usb_rx_empty),
534 .tx_full(usb_tx_full),
535 .rx_data(usb_rx_data),
536 .rx_rdreq(usb_rx_rdreq),
537 .tx_wrreq(usb_tx_wrreq),
538 .tx_data(usb_tx_data),
[90]539 .bus_wren(bus_wren),
540 .bus_addr(bus_addr),
541 .bus_mosi(bus_mosi),
542 .bus_miso(mrg_bus_miso),
543 .bus_busy(mrg_bus_busy),
[59]544 .led(LED));
[45]545
[84]546/*
547 altserial_flash_loader #(
548 .enable_shared_access("OFF"),
549 .enhanced_mode(1),
550 .intended_device_family("Cyclone III")) sfl_unit (
551 .noe(1'b0),
552 .asmi_access_granted(),
553 .asmi_access_request(),
554 .data0out(),
555 .dclkin(),
556 .scein(),
557 .sdoin());
558*/
559
[54]560endmodule
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