Changeset 44 for trunk/MultiChannelUSB/Paella.v
- Timestamp:
- Sep 14, 2009, 12:55:44 AM (15 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/Paella.v (modified) (11 diffs)
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trunk/MultiChannelUSB/Paella.v
r42 r44 111 111 reg [10:0] tst_counter; 112 112 113 reg ana_reset [2:0]; 114 wire ana_peak_ready [2:0]; 115 wire [11:0] ana_peak [2:0]; 116 113 117 reg [9:0] osc_counter; 114 reg osc_reset;115 118 reg osc_byte_num; 116 wire [9:0] osc_start_addr; 117 reg [9:0] osc_addr; 118 wire [15:0] osc_q; 119 120 reg hst_reset; 119 120 reg osc_reset_mux, osc_reset [2:0]; 121 wire [9:0] osc_start_addr [2:0]; 122 reg [9:0] osc_start_addr_mux, osc_addr_mux, osc_addr [2:0]; 123 wire [15:0] osc_q [2:0]; 124 reg [15:0] osc_q_mux; 125 121 126 reg [1:0] hst_byte_num; 122 reg [11:0] hst_addr; 123 wire [31:0] hst_q; 124 125 reg [3:0] state0, state1, state2; 126 reg adc_fifo_rdreq; 127 wire adc_fifo_rdempty; 127 128 reg hst_reset_mux, hst_reset [2:0]; 129 reg [11:0] hst_addr_mux, hst_addr [2:0]; 130 wire [31:0] hst_q [2:0]; 131 reg [31:0] hst_q_mux; 132 133 reg [3:0] select, state1, state2; 128 134 reg adc_fifo_aclr; 129 135 130 reg [31:0] adc_counter;131 reg adc_data_ready;132 136 wire adc_clk; 133 137 134 138 reg [11:0] adc_data; 135 139 140 wire adc_data_ready [2:0]; 136 141 wire [11:0] adc_lvds_data [2:0]; 137 142 138 wire [11:0] raw_data ;139 wire [11:0] uwt_data ;140 wire [1:0] uwt_flag ;143 wire [11:0] raw_data [2:0]; 144 wire [11:0] uwt_data [2:0]; 145 wire [1:0] uwt_flag [2:0]; 141 146 142 147 pll pll_unit( … … 163 168 .adc_dc(adc_lvds_data[1]), 164 169 .adc_dd(adc_lvds_data[2])); 165 166 adc_fifo adc_fifo_unit ( 167 .adc_clk(ADC_FCO), 168 .adc_data(adc_lvds_data[1]), 169 .aclr(adc_fifo_aclr), 170 .rdclk(CLK_50MHz), 171 .rdreq(adc_fifo_rdreq), 172 .rdempty(adc_fifo_rdempty), 173 .raw_data(raw_data), 174 .uwt_data({uwt_flag, uwt_data})); 175 176 histogram histogram_unit ( 177 .clk(CLK_50MHz), 178 .reset(hst_reset), 179 .data_ready(adc_data_ready), 180 .data(raw_data), 181 .address(hst_addr), 182 .q(hst_q)); 170 171 genvar i; 172 generate 173 for (i = 0; i < 3; i = i + 1) 174 begin : MCA_CHAIN 175 adc_fifo adc_fifo_unit ( 176 .adc_clk(ADC_FCO), 177 .adc_data(adc_lvds_data[i]), 178 .aclr(adc_fifo_aclr), 179 .rdclk(CLK_50MHz), 180 .ready(adc_data_ready[i]), 181 .raw_data(raw_data[i]), 182 .uwt_data({uwt_flag[i], uwt_data[i]})); 183 183 184 oscilloscope oscilloscope_unit ( 185 .clk(CLK_50MHz), 186 .reset(osc_reset), 187 .data_ready(adc_data_ready), 188 .raw_data(raw_data), 189 .uwt_data(uwt_data), 190 .threshold(16'd100), 191 .address(osc_addr), 192 .start_address(osc_start_addr), 193 .q(osc_q)); 184 analyser analyser_unit ( 185 .clk(CLK_50MHz), 186 .reset(ana_reset[i]), 187 .data_ready(adc_data_ready[i]), 188 .uwt_flag(uwt_flag[i]), 189 .uwt_data(uwt_data[i]), 190 .peak_ready(ana_peak_ready[i]), 191 .peak(ana_peak[i])); 192 /* 193 histogram histogram_unit ( 194 .clk(CLK_50MHz), 195 .reset(hst_reset[i]), 196 .data_ready(adc_data_ready[i]), 197 .data(raw_data[i]), 198 .address(hst_addr[i]), 199 .q(hst_q[i])); 200 */ 201 histogram histogram_unit ( 202 .clk(CLK_50MHz), 203 .reset(hst_reset[i]), 204 .data_ready(ana_peak_ready[i]), 205 .data(ana_peak[i]), 206 .address(hst_addr[i]), 207 .q(hst_q[i])); 208 209 oscilloscope oscilloscope_unit ( 210 .clk(CLK_50MHz), 211 .reset(osc_reset[i]), 212 .data_ready(adc_data_ready[i]), 213 .raw_data(raw_data[i]), 214 .uwt_data(uwt_data[i]), 215 .threshold(16'd100), 216 .address(osc_addr[i]), 217 .start_address(osc_start_addr[i]), 218 .q(osc_q[i])); 219 end 220 endgenerate 194 221 195 222 /* … … 200 227 */ 201 228 202 always @ (posedge CLK_50MHz)229 always @* 203 230 begin 204 case (state0) 205 1: 206 begin 207 if (~adc_fifo_rdempty) 208 begin 209 // adc_counter <= adc_counter + 32'd1; 210 adc_fifo_rdreq <= 1'b1; 211 adc_data_ready <= 1'b1; 212 state0 <= 4'd2; 213 end 214 end 215 216 2: 217 begin 218 adc_fifo_rdreq <= 1'b0; 219 adc_data_ready <= 1'b0; 220 state0 <= 4'd1; 221 end 222 231 case(select) 232 4'h0: 233 begin 234 osc_reset[0] = osc_reset_mux; 235 osc_addr[0] = osc_addr_mux; 236 osc_q_mux = osc_q[0]; 237 osc_start_addr_mux = osc_start_addr[0]; 238 239 hst_reset[0] = hst_reset_mux; 240 hst_addr[0] = hst_addr_mux; 241 hst_q_mux = hst_q[0]; 242 end 243 4'h1: 244 begin 245 osc_reset[1] = osc_reset_mux; 246 osc_addr[1] = osc_addr_mux; 247 osc_q_mux = osc_q[1]; 248 osc_start_addr_mux = osc_start_addr[1]; 249 250 hst_reset[1] = hst_reset_mux; 251 hst_addr[1] = hst_addr_mux; 252 hst_q_mux = hst_q[1]; 253 end 254 4'h2: 255 begin 256 osc_reset[2] = osc_reset_mux; 257 osc_addr[2] = osc_addr_mux; 258 osc_q_mux = osc_q[2]; 259 osc_start_addr_mux = osc_start_addr[2]; 260 261 hst_reset[2] = hst_reset_mux; 262 hst_addr[2] = hst_addr_mux; 263 hst_q_mux = hst_q[2]; 264 end 223 265 default: 224 266 begin 225 state0 <= 4'd1; 267 osc_reset[0] = osc_reset_mux; 268 osc_addr[0] = osc_addr_mux; 269 osc_q_mux = osc_q[0]; 270 osc_start_addr_mux = osc_start_addr[0]; 271 272 hst_reset[0] = hst_reset_mux; 273 hst_addr[0] = hst_addr_mux; 274 hst_q_mux = hst_q[0]; 226 275 end 227 276 endcase … … 252 301 usb_fifo_rx_rdreq <= 1'b1; 253 302 usb_fifo_tx_wrreq <= 1'b0; 254 hst_reset <= 1'b0;255 osc_reset <= 1'b0;303 hst_reset_mux <= 1'b0; 304 osc_reset_mux <= 1'b0; 256 305 state1 <= 4'd2; 257 306 end … … 262 311 begin 263 312 case (usb_fifo_rx_data) 264 8'h 30:313 8'h40, 8'h41, 8'h42: 265 314 begin 266 315 usb_fifo_rx_rdreq <= 1'b0; 267 hst_reset <= 1'b1; 316 hst_reset_mux <= 1'b1; 317 select <= usb_fifo_rx_data[3:0]; 268 318 state1 <= 4'd1; 269 319 end 270 8'h 31:320 8'h50, 8'h51, 8'h52: 271 321 begin 272 322 usb_fifo_rx_rdreq <= 1'b0; 273 hst_addr <= 12'd0;323 hst_addr_mux <= 12'd0; 274 324 hst_byte_num <= 2'd0; 325 select <= usb_fifo_rx_data[3:0]; 275 326 state1 <= 4'd3; 276 327 end 277 8'h 32:328 8'h60, 8'h61, 8'h62: 278 329 begin 279 330 usb_fifo_rx_rdreq <= 1'b0; 280 osc_reset <= 1'b1; 331 osc_reset_mux <= 1'b1; 332 select <= usb_fifo_rx_data[3:0]; 281 333 state1 <= 4'd1; 282 334 end 283 8'h 33:335 8'h70, 8'h71, 8'h72: 284 336 begin 285 337 usb_fifo_rx_rdreq <= 1'b0; 286 osc_addr <= osc_start_addr;338 osc_addr_mux <= osc_start_addr_mux; 287 339 osc_counter <= 10'd0; 288 340 osc_byte_num <= 1'd0; 341 select <= usb_fifo_rx_data[3:0]; 289 342 state1 <= 4'd6; 290 343 end 291 8'h3 4:344 8'h30: 292 345 begin 293 346 usb_fifo_rx_rdreq <= 1'b0; 294 347 state1 <= 4'd1; 295 348 end 296 8'h3 5:349 8'h31: 297 350 begin 298 351 usb_fifo_rx_rdreq <= 1'b0; … … 307 360 3: 308 361 begin 309 usb_fifo_tx_data <= hst_q [7:0];362 usb_fifo_tx_data <= hst_q_mux[7:0]; 310 363 usb_fifo_tx_wrreq <= 1'b1; 311 364 hst_byte_num <= 2'd1; … … 317 370 begin 318 371 case (hst_byte_num) 319 2'd0: usb_fifo_tx_data <= hst_q [7:0];320 2'd1: usb_fifo_tx_data <= hst_q [15:8];321 2'd2: usb_fifo_tx_data <= hst_q [23:16];322 2'd3: usb_fifo_tx_data <= hst_q [31:24];372 2'd0: usb_fifo_tx_data <= hst_q_mux[7:0]; 373 2'd1: usb_fifo_tx_data <= hst_q_mux[15:8]; 374 2'd2: usb_fifo_tx_data <= hst_q_mux[23:16]; 375 2'd3: usb_fifo_tx_data <= hst_q_mux[31:24]; 323 376 endcase 324 if ((&hst_byte_num) & (&hst_addr ))377 if ((&hst_byte_num) & (&hst_addr_mux)) 325 378 begin 326 379 state1 <= 4'd5; … … 330 383 if (&hst_byte_num) 331 384 begin 332 hst_addr <= hst_addr+ 12'd1;385 hst_addr_mux <= hst_addr_mux + 12'd1; 333 386 end 334 387 hst_byte_num <= hst_byte_num + 2'd1; … … 348 401 6: 349 402 begin 350 usb_fifo_tx_data <= osc_q [7:0];403 usb_fifo_tx_data <= osc_q_mux[7:0]; 351 404 usb_fifo_tx_wrreq <= 1'b1; 352 405 osc_byte_num <= 1'd1; … … 358 411 begin 359 412 case (osc_byte_num) 360 1'd0: usb_fifo_tx_data <= osc_q [7:0];361 1'd1: usb_fifo_tx_data <= osc_q [15:8];413 1'd0: usb_fifo_tx_data <= osc_q_mux[7:0]; 414 1'd1: usb_fifo_tx_data <= osc_q_mux[15:8]; 362 415 endcase 363 416 if ((&osc_byte_num) & (&osc_counter)) … … 369 422 if (&osc_byte_num) 370 423 begin 371 osc_addr <= osc_addr+ 10'd1;424 osc_addr_mux <= osc_addr_mux + 10'd1; 372 425 osc_counter <= osc_counter + 10'd1; 373 426 end
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