Changeset 45 for trunk/MultiChannelUSB/Paella.v

Timestamp:

Sep 15, 2009, 3:27:35 AM (15 years ago)

Author:

demin

Message:

add fourth channel and switch from 32 to 24 bit histogram

File:

• trunk/MultiChannelUSB/Paella.v (modified) (12 diffs)

trunk/MultiChannelUSB/Paella.v

@@ -111 +111 @@
         reg             [10:0]  tst_counter;    
 
-        reg                     ana_reset [2:0];
-        wire                    ana_peak_ready [2:0];
-        wire    [11:0]  ana_peak [2:0];
+        reg                     ana_reset [3:0];
+        wire                    ana_peak_ready [3:0];
+        wire    [11:0]  ana_peak [3:0];
 
         reg             [9:0]   osc_counter;    
-        reg                     osc_byte_num;
-
-        reg                     osc_reset_mux, osc_reset [2:0];
-        wire    [9:0]   osc_start_addr [2:0];
-        reg     [9:0]   osc_start_addr_mux, osc_addr_mux, osc_addr [2:0];
-        wire    [15:0]  osc_q [2:0];
+
+        reg                     osc_reset [3:0];
+        wire    [9:0]   osc_start_addr [3:0];
+        reg     [9:0]   osc_addr [3:0];
+        wire    [15:0]  osc_q [3:0];
         reg             [15:0]  osc_q_mux;
 
-        reg     [1:0]   hst_byte_num;
-
-        reg                     hst_reset_mux, hst_reset [2:0];
-        reg     [11:0]  hst_addr_mux, hst_addr [2:0];
-        wire    [31:0]  hst_q [2:0];
-        reg             [31:0]  hst_q_mux;
-
-        reg             [3:0]   select, state1, state2;
+        reg                     hst_reset [3:0];
+        reg     [11:0]  hst_addr [3:0];
+        wire    [23:0]  hst_q [3:0];
+
+        reg                     mux_reset, mux_type;
+        reg     [1:0]   mux_chan, mux_byte, mux_max_byte;
+        reg     [15:0]  mux_addr, mux_min_addr, mux_max_addr;
+        reg             [7:0]   mux_q;
+
+        reg             [3:0]   state1, state2;
         reg                             adc_fifo_aclr;
 
-        wire                    adc_clk;
-
-        reg     [11:0]  adc_data;
-
-        wire                    adc_data_ready [2:0];
-        wire    [11:0]  adc_lvds_data [2:0];
-
-    wire        [11:0]  raw_data [2:0];
-    wire        [11:0]  uwt_data [2:0];
-    wire        [1:0]   uwt_flag [2:0];
- 
+        wire                    adc_clk [3:0];
+
+//      reg     [11:0]  adc_data;
+
+        wire                    adc_data_ready [3:0];
+        wire    [11:0]  adc_data [3:0];
+
+    wire        [11:0]  raw_data [3:0];
+    wire        [11:0]  uwt_data [3:0];
+    wire        [1:0]   uwt_flag [3:0];
+    
+    assign      adc_clk[0] = ADC_FCO;
+    assign      adc_clk[1] = ADC_FCO;
+    assign      adc_clk[2] = ADC_FCO;
+    assign      adc_clk[3] = CON_B[0];
+    assign      adc_data[3] = CON_B[12:1];
+/* 
         pll pll_unit(
                 .inclk0(CLK_50MHz),
                 .c0(adc_clk));
+*/
 /*
         altserial_flash_loader #(
@@ -165 +173 @@
                 .lvds_fco(ADC_FCO),
                 .lvds_d(ADC_D),
-                .adc_db(adc_lvds_data[0]),
-                .adc_dc(adc_lvds_data[1]),
-                .adc_dd(adc_lvds_data[2]));
+                .adc_db(adc_data[0]),
+                .adc_dc(adc_data[1]),
+                .adc_dd(adc_data[2]));
  
         genvar i;
         generate
-                for (i = 0; i < 3; i = i + 1)
+                for (i = 0; i < 4; i = i + 1)
                 begin : MCA_CHAIN
                         adc_fifo adc_fifo_unit (
-                                .adc_clk(ADC_FCO),
-                                .adc_data(adc_lvds_data[i]),
+                                .adc_clk(adc_clk[i]),
+                                .adc_data(adc_data[i]),
                                 .aclr(adc_fifo_aclr),
                                 .rdclk(CLK_50MHz),
@@ -229 +237 @@
         always @*
         begin
-                case(select)
-                        4'h0:
-                        begin
-                                osc_reset[0] = osc_reset_mux;
-                                osc_addr[0] = osc_addr_mux;
-                                osc_q_mux = osc_q[0];
-                                osc_start_addr_mux = osc_start_addr[0];
-                                
-                                hst_reset[0] = hst_reset_mux;
-                                hst_addr[0] = hst_addr_mux;
-                                hst_q_mux = hst_q[0];
-                        end
-                        4'h1:
-                        begin
-                                osc_reset[1] = osc_reset_mux;
-                                osc_addr[1] = osc_addr_mux;
-                                osc_q_mux = osc_q[1];
-                                osc_start_addr_mux = osc_start_addr[1];
-                                
-                                hst_reset[1] = hst_reset_mux;
-                                hst_addr[1] = hst_addr_mux;
-                                hst_q_mux = hst_q[1];
-                        end
-                        4'h2:
-                        begin
-                                osc_reset[2] = osc_reset_mux;
-                                osc_addr[2] = osc_addr_mux;
-                                osc_q_mux = osc_q[2];
-                                osc_start_addr_mux = osc_start_addr[2];
-                                
-                                hst_reset[2] = hst_reset_mux;
-                                hst_addr[2] = hst_addr_mux;
-                                hst_q_mux = hst_q[2];
-                        end
-                        default:
-                        begin
-                                osc_reset[0] = osc_reset_mux;
-                                osc_addr[0] = osc_addr_mux;
-                                osc_q_mux = osc_q[0];
-                                osc_start_addr_mux = osc_start_addr[0];
-                                
-                                hst_reset[0] = hst_reset_mux;
-                                hst_addr[0] = hst_addr_mux;
-                                hst_q_mux = hst_q[0];
+                osc_reset[0] = 1'b0;
+                osc_addr[0] = 10'b0;
+                osc_reset[1] = 1'b0;
+                osc_addr[1] = 10'b0;
+                osc_reset[2] = 1'b0;
+                osc_addr[2] = 10'b0;
+                osc_reset[3] = 1'b0;
+                osc_addr[3] = 10'b0;
+                hst_reset[0] = 1'b0;
+                hst_addr[0] = 12'b0;
+                hst_reset[1] = 1'b0;
+                hst_addr[1] = 12'b0;
+                hst_reset[2] = 1'b0;
+                hst_addr[2] = 12'b0;
+                hst_reset[3] = 1'b0;
+                hst_addr[3] = 12'b0;
+                case({mux_type,mux_chan})
+                        3'b000, 3'b001, 3'b010, 3'b011:
+                        begin
+                                osc_reset[mux_chan] = mux_reset;
+                                osc_addr[mux_chan] = mux_addr[9:0];
+                                mux_max_byte = 2'd1;    
+                                mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
+                                mux_max_addr = {6'd0, osc_start_addr[mux_chan]} + 16'd1023;
+                        end
+
+                        3'b100, 3'b101, 3'b110, 3'b111:
+                        begin
+                                hst_reset[mux_chan] = mux_reset;
+                                hst_addr[mux_chan] = mux_addr[11:0];
+                                mux_max_byte = 2'd2;    
+                                mux_min_addr = 16'd0;
+                                mux_max_addr = 16'd4095;
                         end
                 endcase
         end
+        
+        always @*
+        begin
+                case ({mux_type,mux_byte})
+                        5'b000: mux_q = osc_q[mux_chan][7:0];
+                        5'b001: mux_q = osc_q[mux_chan][15:8];
+
+                        5'b100: mux_q = hst_q[mux_chan][7:0];
+                        5'b101: mux_q = hst_q[mux_chan][15:8];
+                        5'b110: mux_q = hst_q[mux_chan][23:16];
+
+                        default: mux_q = 8'd0;
+                endcase     
+        end
+
 
         always @(posedge CLK_50MHz)
@@ -301 +313 @@
                                 usb_fifo_rx_rdreq <= 1'b1;
                                 usb_fifo_tx_wrreq <= 1'b0;
-                                hst_reset_mux <= 1'b0;
-                                osc_reset_mux <= 1'b0;
+                                mux_type <= 1'b0;
+                                mux_chan <= 2'd0;
+                                mux_byte <= 2'd0;       
+                                mux_reset <= 1'b0;
                                 state1 <= 4'd2;
                         end
@@ -311 +325 @@
                                 begin
                                         case (usb_fifo_rx_data)
-                                                8'h40, 8'h41, 8'h42:
+                                                8'h40, 8'h41, 8'h42, 8'h43, 8'h50, 8'h51, 8'h52, 8'h53:
                                                 begin
                                                         usb_fifo_rx_rdreq <= 1'b0;
-                                                        hst_reset_mux <= 1'b1;
-                                                        select <= usb_fifo_rx_data[3:0];
+                                                        mux_type <= usb_fifo_rx_data[4];
+                                                        mux_chan <= usb_fifo_rx_data[1:0];
+                                                        mux_reset <= 1'b1;
                                                         state1 <= 4'd1;
                                                 end
-                                                8'h50, 8'h51, 8'h52:
+
+                                                8'h60, 8'h61, 8'h62, 8'h63, 8'h70, 8'h71, 8'h72, 8'h73:
                                                 begin
                                                         usb_fifo_rx_rdreq <= 1'b0;
-                                                        hst_addr_mux <= 12'd0;
-                                                        hst_byte_num <= 2'd0;   
-                                                        select <= usb_fifo_rx_data[3:0];
+                                                        mux_type <= usb_fifo_rx_data[4];
+                                                        mux_chan <= usb_fifo_rx_data[1:0];
                                                         state1 <= 4'd3;
                                                 end
-                                                8'h60, 8'h61, 8'h62:
-                                                begin
-                                                        usb_fifo_rx_rdreq <= 1'b0;
-                                                        osc_reset_mux <= 1'b1;
-                                                        select <= usb_fifo_rx_data[3:0];
-                                                        state1 <= 4'd1;
-                                                end
-                                                8'h70, 8'h71, 8'h72:
-                                                begin
-                                                        usb_fifo_rx_rdreq <= 1'b0;
-                                                        osc_addr_mux <= osc_start_addr_mux;
-                                                        osc_counter <= 10'd0;
-                                                        osc_byte_num <= 1'd0;   
-                                                        select <= usb_fifo_rx_data[3:0];
-                                                        state1 <= 4'd6;
-                                                end
+
                                                 8'h30:
                                                 begin
@@ -347 +347 @@
                                                         state1 <= 4'd1;
                                                 end
+
                                                 8'h31:
                                                 begin
@@ -356 +357 @@
                                 end
                         end
-
-                        // hst transfer
+                        // mux transfer
                         3:
                         begin
-                                usb_fifo_tx_data <= hst_q_mux[7:0];
+                                mux_addr <= mux_min_addr;
+                                mux_byte <= 2'd0;       
+                                state1 <= 4'd4;
+                        end
+                        4:
+                        begin
+                                usb_fifo_tx_data <= mux_q;
                                 usb_fifo_tx_wrreq <= 1'b1;
-                                hst_byte_num <= 2'd1;
-                                state1 <= 4'd4;
-                        end
-                        4:
+                                mux_byte <= 2'd1;
+                                state1 <= 4'd5;
+                        end
+                        5:
                         begin
                                 if (~usb_fifo_tx_full)
                                 begin
-                                        case (hst_byte_num)
-                                                2'd0: usb_fifo_tx_data <= hst_q_mux[7:0];
-                                                2'd1: usb_fifo_tx_data <= hst_q_mux[15:8];
-                                                2'd2: usb_fifo_tx_data <= hst_q_mux[23:16];
-                                                2'd3: usb_fifo_tx_data <= hst_q_mux[31:24];
-                                        endcase
-                                        if ((&hst_byte_num) & (&hst_addr_mux))
+                                        usb_fifo_tx_data <= mux_q;
+                                        if ((mux_byte == mux_max_byte) && (mux_addr == mux_max_addr))
                                         begin
-                                                state1 <= 4'd5;
+                                                state1 <= 4'd6;
                                         end
                                         else
                                         begin
-                                                if (&hst_byte_num)
-                                                begin
-                                                        hst_addr_mux <= hst_addr_mux + 12'd1;
-                                                end
-                                                hst_byte_num <= hst_byte_num + 2'd1;
+                                                if (mux_byte == mux_max_byte)
+                                                begin
+                                                        mux_addr <= mux_addr + 16'd1;
+                                                        mux_byte <= 2'd0;
+                                                end
+                                                else
+                                                begin
+                                                        mux_byte <= mux_byte + 2'd1;
+                                                end
                                         end
                                 end
                         end
-                        5:
+                        6:
                         begin
                                 if (~usb_fifo_tx_full)
@@ -397 +402 @@
                                 end
                         end
-
-                        // osc transfer
-                        6:
-                        begin
-                                usb_fifo_tx_data <= osc_q_mux[7:0];
-                                usb_fifo_tx_wrreq <= 1'b1;
-                                osc_byte_num <= 1'd1;
-                                state1 <= 4'd7;
-                        end
+                        // tst transfer
                         7:
-                        begin
-                                if (~usb_fifo_tx_full)
-                                begin
-                                        case (osc_byte_num)
-                                                1'd0: usb_fifo_tx_data <= osc_q_mux[7:0];
-                                                1'd1: usb_fifo_tx_data <= osc_q_mux[15:8];
-                                        endcase
-                                        if ((&osc_byte_num) & (&osc_counter))
-                                        begin
-                                                state1 <= 4'd8;
-                                        end
-                                        else
-                                        begin
-                                                if (&osc_byte_num)
-                                                begin
-                                                        osc_addr_mux <= osc_addr_mux + 10'd1;
-                                                        osc_counter <= osc_counter + 10'd1;
-                                                end
-                                                osc_byte_num <= osc_byte_num + 1'd1;
-                                        end
-                                end
-                        end
-                        8:
-                        begin
-                                if (~usb_fifo_tx_full)
-                                begin
-                                        usb_fifo_tx_wrreq <= 1'b0;
-                                        state1 <= 4'd1;
-                                end
-                        end
-                        // tst transfer
-                        9:
                         begin
                                 usb_fifo_tx_data <= tst_counter;
                                 usb_fifo_tx_wrreq <= 1'b1;
                                 tst_counter <= tst_counter + 11'd1;
-                                state1 <= 4'd10;
-                        end
-                        10:
+                                state1 <= 4'd8;
+                        end
+                        8:
                         begin
                                 if (~usb_fifo_tx_full)
@@ -452 +417 @@
                                         if (tst_counter == 11'd0) //(&osc_counter)
                                         begin
-                                                state1 <= 4'd11;
+                                                state1 <= 4'd9;
                                         end
                                         else
@@ -460 +425 @@
                                 end
                         end
-                        11:
+                        9:
                         begin
                                 if (~usb_fifo_tx_full)
@@ -475 +440 @@
                 endcase
         end
-
+/*
         always @ (posedge adc_clk)
         begin
@@ -515 +480 @@
                 endcase
         end
-
+*/
 endmodule