Changeset 45
- Timestamp:
- Sep 15, 2009, 3:27:35 AM (15 years ago)
- Location:
- trunk/MultiChannelUSB
- Files:
-
- 1 added
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/MultiChannelUSB/Paella.qsf
r44 r45 47 47 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 48 48 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF 49 50 set_global_assignment -name VERILOG_FILE adc_fifo.v 50 51 set_global_assignment -name VERILOG_FILE adc_lvds.v 51 set_global_assignment -name VERILOG_FILE fifo32x8.v52 set_global_assignment -name VERILOG_FILE fifo32x12.v53 set_global_assignment -name VERILOG_FILE fifo32x14.v54 52 set_global_assignment -name VERILOG_FILE analyser.v 55 53 set_global_assignment -name VERILOG_FILE histogram.v … … 57 55 set_global_assignment -name VERILOG_FILE pll.v 58 56 set_global_assignment -name VERILOG_FILE ram1024x16.v 59 set_global_assignment -name VERILOG_FILE ram4096x 32.v57 set_global_assignment -name VERILOG_FILE ram4096x24.v 60 58 set_global_assignment -name VERILOG_FILE usb_fifo.v 61 59 set_global_assignment -name VERILOG_FILE uwt_bior31.v -
trunk/MultiChannelUSB/Paella.v
r44 r45 111 111 reg [10:0] tst_counter; 112 112 113 reg ana_reset [ 2:0];114 wire ana_peak_ready [ 2:0];115 wire [11:0] ana_peak [ 2:0];113 reg ana_reset [3:0]; 114 wire ana_peak_ready [3:0]; 115 wire [11:0] ana_peak [3:0]; 116 116 117 117 reg [9:0] osc_counter; 118 reg osc_byte_num; 119 120 reg osc_reset_mux, osc_reset [2:0]; 121 wire [9:0] osc_start_addr [2:0]; 122 reg [9:0] osc_start_addr_mux, osc_addr_mux, osc_addr [2:0]; 123 wire [15:0] osc_q [2:0]; 118 119 reg osc_reset [3:0]; 120 wire [9:0] osc_start_addr [3:0]; 121 reg [9:0] osc_addr [3:0]; 122 wire [15:0] osc_q [3:0]; 124 123 reg [15:0] osc_q_mux; 125 124 126 reg [1:0] hst_byte_num; 127 128 reg hst_reset_mux, hst_reset [2:0]; 129 reg [11:0] hst_addr_mux, hst_addr [2:0]; 130 wire [31:0] hst_q [2:0]; 131 reg [31:0] hst_q_mux; 132 133 reg [3:0] select, state1, state2; 125 reg hst_reset [3:0]; 126 reg [11:0] hst_addr [3:0]; 127 wire [23:0] hst_q [3:0]; 128 129 reg mux_reset, mux_type; 130 reg [1:0] mux_chan, mux_byte, mux_max_byte; 131 reg [15:0] mux_addr, mux_min_addr, mux_max_addr; 132 reg [7:0] mux_q; 133 134 reg [3:0] state1, state2; 134 135 reg adc_fifo_aclr; 135 136 136 wire adc_clk; 137 138 reg [11:0] adc_data; 139 140 wire adc_data_ready [2:0]; 141 wire [11:0] adc_lvds_data [2:0]; 142 143 wire [11:0] raw_data [2:0]; 144 wire [11:0] uwt_data [2:0]; 145 wire [1:0] uwt_flag [2:0]; 146 137 wire adc_clk [3:0]; 138 139 // reg [11:0] adc_data; 140 141 wire adc_data_ready [3:0]; 142 wire [11:0] adc_data [3:0]; 143 144 wire [11:0] raw_data [3:0]; 145 wire [11:0] uwt_data [3:0]; 146 wire [1:0] uwt_flag [3:0]; 147 148 assign adc_clk[0] = ADC_FCO; 149 assign adc_clk[1] = ADC_FCO; 150 assign adc_clk[2] = ADC_FCO; 151 assign adc_clk[3] = CON_B[0]; 152 assign adc_data[3] = CON_B[12:1]; 153 /* 147 154 pll pll_unit( 148 155 .inclk0(CLK_50MHz), 149 156 .c0(adc_clk)); 157 */ 150 158 /* 151 159 altserial_flash_loader #( … … 165 173 .lvds_fco(ADC_FCO), 166 174 .lvds_d(ADC_D), 167 .adc_db(adc_ lvds_data[0]),168 .adc_dc(adc_ lvds_data[1]),169 .adc_dd(adc_ lvds_data[2]));175 .adc_db(adc_data[0]), 176 .adc_dc(adc_data[1]), 177 .adc_dd(adc_data[2])); 170 178 171 179 genvar i; 172 180 generate 173 for (i = 0; i < 3; i = i + 1)181 for (i = 0; i < 4; i = i + 1) 174 182 begin : MCA_CHAIN 175 183 adc_fifo adc_fifo_unit ( 176 .adc_clk( ADC_FCO),177 .adc_data(adc_ lvds_data[i]),184 .adc_clk(adc_clk[i]), 185 .adc_data(adc_data[i]), 178 186 .aclr(adc_fifo_aclr), 179 187 .rdclk(CLK_50MHz), … … 229 237 always @* 230 238 begin 231 case(select) 232 4'h0: 233 begin 234 osc_reset[0] = osc_reset_mux; 235 osc_addr[0] = osc_addr_mux; 236 osc_q_mux = osc_q[0]; 237 osc_start_addr_mux = osc_start_addr[0]; 238 239 hst_reset[0] = hst_reset_mux; 240 hst_addr[0] = hst_addr_mux; 241 hst_q_mux = hst_q[0]; 242 end 243 4'h1: 244 begin 245 osc_reset[1] = osc_reset_mux; 246 osc_addr[1] = osc_addr_mux; 247 osc_q_mux = osc_q[1]; 248 osc_start_addr_mux = osc_start_addr[1]; 249 250 hst_reset[1] = hst_reset_mux; 251 hst_addr[1] = hst_addr_mux; 252 hst_q_mux = hst_q[1]; 253 end 254 4'h2: 255 begin 256 osc_reset[2] = osc_reset_mux; 257 osc_addr[2] = osc_addr_mux; 258 osc_q_mux = osc_q[2]; 259 osc_start_addr_mux = osc_start_addr[2]; 260 261 hst_reset[2] = hst_reset_mux; 262 hst_addr[2] = hst_addr_mux; 263 hst_q_mux = hst_q[2]; 264 end 265 default: 266 begin 267 osc_reset[0] = osc_reset_mux; 268 osc_addr[0] = osc_addr_mux; 269 osc_q_mux = osc_q[0]; 270 osc_start_addr_mux = osc_start_addr[0]; 271 272 hst_reset[0] = hst_reset_mux; 273 hst_addr[0] = hst_addr_mux; 274 hst_q_mux = hst_q[0]; 239 osc_reset[0] = 1'b0; 240 osc_addr[0] = 10'b0; 241 osc_reset[1] = 1'b0; 242 osc_addr[1] = 10'b0; 243 osc_reset[2] = 1'b0; 244 osc_addr[2] = 10'b0; 245 osc_reset[3] = 1'b0; 246 osc_addr[3] = 10'b0; 247 hst_reset[0] = 1'b0; 248 hst_addr[0] = 12'b0; 249 hst_reset[1] = 1'b0; 250 hst_addr[1] = 12'b0; 251 hst_reset[2] = 1'b0; 252 hst_addr[2] = 12'b0; 253 hst_reset[3] = 1'b0; 254 hst_addr[3] = 12'b0; 255 case({mux_type,mux_chan}) 256 3'b000, 3'b001, 3'b010, 3'b011: 257 begin 258 osc_reset[mux_chan] = mux_reset; 259 osc_addr[mux_chan] = mux_addr[9:0]; 260 mux_max_byte = 2'd1; 261 mux_min_addr = {6'd0, osc_start_addr[mux_chan]}; 262 mux_max_addr = {6'd0, osc_start_addr[mux_chan]} + 16'd1023; 263 end 264 265 3'b100, 3'b101, 3'b110, 3'b111: 266 begin 267 hst_reset[mux_chan] = mux_reset; 268 hst_addr[mux_chan] = mux_addr[11:0]; 269 mux_max_byte = 2'd2; 270 mux_min_addr = 16'd0; 271 mux_max_addr = 16'd4095; 275 272 end 276 273 endcase 277 274 end 275 276 always @* 277 begin 278 case ({mux_type,mux_byte}) 279 5'b000: mux_q = osc_q[mux_chan][7:0]; 280 5'b001: mux_q = osc_q[mux_chan][15:8]; 281 282 5'b100: mux_q = hst_q[mux_chan][7:0]; 283 5'b101: mux_q = hst_q[mux_chan][15:8]; 284 5'b110: mux_q = hst_q[mux_chan][23:16]; 285 286 default: mux_q = 8'd0; 287 endcase 288 end 289 278 290 279 291 always @(posedge CLK_50MHz) … … 301 313 usb_fifo_rx_rdreq <= 1'b1; 302 314 usb_fifo_tx_wrreq <= 1'b0; 303 hst_reset_mux <= 1'b0; 304 osc_reset_mux <= 1'b0; 315 mux_type <= 1'b0; 316 mux_chan <= 2'd0; 317 mux_byte <= 2'd0; 318 mux_reset <= 1'b0; 305 319 state1 <= 4'd2; 306 320 end … … 311 325 begin 312 326 case (usb_fifo_rx_data) 313 8'h40, 8'h41, 8'h42 :327 8'h40, 8'h41, 8'h42, 8'h43, 8'h50, 8'h51, 8'h52, 8'h53: 314 328 begin 315 329 usb_fifo_rx_rdreq <= 1'b0; 316 hst_reset_mux <= 1'b1; 317 select <= usb_fifo_rx_data[3:0]; 330 mux_type <= usb_fifo_rx_data[4]; 331 mux_chan <= usb_fifo_rx_data[1:0]; 332 mux_reset <= 1'b1; 318 333 state1 <= 4'd1; 319 334 end 320 8'h50, 8'h51, 8'h52: 335 336 8'h60, 8'h61, 8'h62, 8'h63, 8'h70, 8'h71, 8'h72, 8'h73: 321 337 begin 322 338 usb_fifo_rx_rdreq <= 1'b0; 323 hst_addr_mux <= 12'd0; 324 hst_byte_num <= 2'd0; 325 select <= usb_fifo_rx_data[3:0]; 339 mux_type <= usb_fifo_rx_data[4]; 340 mux_chan <= usb_fifo_rx_data[1:0]; 326 341 state1 <= 4'd3; 327 342 end 328 8'h60, 8'h61, 8'h62: 329 begin 330 usb_fifo_rx_rdreq <= 1'b0; 331 osc_reset_mux <= 1'b1; 332 select <= usb_fifo_rx_data[3:0]; 333 state1 <= 4'd1; 334 end 335 8'h70, 8'h71, 8'h72: 336 begin 337 usb_fifo_rx_rdreq <= 1'b0; 338 osc_addr_mux <= osc_start_addr_mux; 339 osc_counter <= 10'd0; 340 osc_byte_num <= 1'd0; 341 select <= usb_fifo_rx_data[3:0]; 342 state1 <= 4'd6; 343 end 343 344 344 8'h30: 345 345 begin … … 347 347 state1 <= 4'd1; 348 348 end 349 349 350 8'h31: 350 351 begin … … 356 357 end 357 358 end 358 359 // hst transfer 359 // mux transfer 360 360 3: 361 361 begin 362 usb_fifo_tx_data <= hst_q_mux[7:0]; 362 mux_addr <= mux_min_addr; 363 mux_byte <= 2'd0; 364 state1 <= 4'd4; 365 end 366 4: 367 begin 368 usb_fifo_tx_data <= mux_q; 363 369 usb_fifo_tx_wrreq <= 1'b1; 364 hst_byte_num<= 2'd1;365 state1 <= 4'd 4;366 end 367 4:370 mux_byte <= 2'd1; 371 state1 <= 4'd5; 372 end 373 5: 368 374 begin 369 375 if (~usb_fifo_tx_full) 370 376 begin 371 case (hst_byte_num) 372 2'd0: usb_fifo_tx_data <= hst_q_mux[7:0]; 373 2'd1: usb_fifo_tx_data <= hst_q_mux[15:8]; 374 2'd2: usb_fifo_tx_data <= hst_q_mux[23:16]; 375 2'd3: usb_fifo_tx_data <= hst_q_mux[31:24]; 376 endcase 377 if ((&hst_byte_num) & (&hst_addr_mux)) 377 usb_fifo_tx_data <= mux_q; 378 if ((mux_byte == mux_max_byte) && (mux_addr == mux_max_addr)) 378 379 begin 379 state1 <= 4'd 5;380 state1 <= 4'd6; 380 381 end 381 382 else 382 383 begin 383 if (&hst_byte_num) 384 begin 385 hst_addr_mux <= hst_addr_mux + 12'd1; 386 end 387 hst_byte_num <= hst_byte_num + 2'd1; 384 if (mux_byte == mux_max_byte) 385 begin 386 mux_addr <= mux_addr + 16'd1; 387 mux_byte <= 2'd0; 388 end 389 else 390 begin 391 mux_byte <= mux_byte + 2'd1; 392 end 388 393 end 389 394 end 390 395 end 391 5:396 6: 392 397 begin 393 398 if (~usb_fifo_tx_full) … … 397 402 end 398 403 end 399 400 // osc transfer 401 6: 402 begin 403 usb_fifo_tx_data <= osc_q_mux[7:0]; 404 usb_fifo_tx_wrreq <= 1'b1; 405 osc_byte_num <= 1'd1; 406 state1 <= 4'd7; 407 end 404 // tst transfer 408 405 7: 409 begin410 if (~usb_fifo_tx_full)411 begin412 case (osc_byte_num)413 1'd0: usb_fifo_tx_data <= osc_q_mux[7:0];414 1'd1: usb_fifo_tx_data <= osc_q_mux[15:8];415 endcase416 if ((&osc_byte_num) & (&osc_counter))417 begin418 state1 <= 4'd8;419 end420 else421 begin422 if (&osc_byte_num)423 begin424 osc_addr_mux <= osc_addr_mux + 10'd1;425 osc_counter <= osc_counter + 10'd1;426 end427 osc_byte_num <= osc_byte_num + 1'd1;428 end429 end430 end431 8:432 begin433 if (~usb_fifo_tx_full)434 begin435 usb_fifo_tx_wrreq <= 1'b0;436 state1 <= 4'd1;437 end438 end439 // tst transfer440 9:441 406 begin 442 407 usb_fifo_tx_data <= tst_counter; 443 408 usb_fifo_tx_wrreq <= 1'b1; 444 409 tst_counter <= tst_counter + 11'd1; 445 state1 <= 4'd 10;446 end 447 10:410 state1 <= 4'd8; 411 end 412 8: 448 413 begin 449 414 if (~usb_fifo_tx_full) … … 452 417 if (tst_counter == 11'd0) //(&osc_counter) 453 418 begin 454 state1 <= 4'd 11;419 state1 <= 4'd9; 455 420 end 456 421 else … … 460 425 end 461 426 end 462 11:427 9: 463 428 begin 464 429 if (~usb_fifo_tx_full) … … 475 440 endcase 476 441 end 477 442 /* 478 443 always @ (posedge adc_clk) 479 444 begin … … 515 480 endcase 516 481 end 517 482 */ 518 483 endmodule -
trunk/MultiChannelUSB/adc_fifo.v
r44 r45 47 47 .flag(uwt_flag3)); 48 48 49 50 fifo32x12 fifo0 ( 49 dcfifo #( 50 .intended_device_family("Cyclone III"), 51 .lpm_numwords(16), 52 .lpm_showahead("ON"), 53 .lpm_type("dcfifo"), 54 .lpm_width(12), 55 .lpm_widthu(4), 56 .rdsync_delaypipe(4), 57 .wrsync_delaypipe(4), 58 .overflow_checking("ON"), 59 .underflow_checking("ON"), 60 .use_eab("OFF"), 61 .write_aclr_synch("OFF")) fifo_raw ( 51 62 .aclr(aclr), 52 63 .data(adc_data), … … 57 68 .q(raw_data), 58 69 .rdempty(int_rdempty), 59 .wrfull(wrfull[0])); 70 .wrfull(wrfull[0]), 71 .rdfull(), 72 .rdusedw(), 73 .wrempty(), 74 .wrusedw()); 60 75 61 fifo32x14 fifo1 ( 76 dcfifo #( 77 .intended_device_family("Cyclone III"), 78 .lpm_numwords(16), 79 .lpm_showahead("ON"), 80 .lpm_type("dcfifo"), 81 .lpm_width(14), 82 .lpm_widthu(4), 83 .rdsync_delaypipe(4), 84 .wrsync_delaypipe(4), 85 .overflow_checking("ON"), 86 .underflow_checking("ON"), 87 .use_eab("OFF"), 88 .write_aclr_synch("OFF")) fifo_uwt ( 62 89 .aclr(aclr), 63 90 .data({uwt_flag3, uwt_peak3[11:0]}), … … 68 95 .q(uwt_data), 69 96 .rdempty(), 70 .wrfull(wrfull[1])); 97 .wrfull(wrfull[1]), 98 .rdfull(), 99 .rdusedw(), 100 .wrempty(), 101 .wrusedw()); 71 102 72 103 always @ (posedge rdclk) -
trunk/MultiChannelUSB/analyser.v
r44 r45 68 68 if (&counter_reg) 69 69 begin 70 state_next <= 2'd1;70 state_next = 2'd1; 71 71 end 72 72 end … … 80 80 if (&counter_reg) 81 81 begin 82 state_next <= 2'd2;82 state_next = 2'd2; 83 83 end 84 84 end -
trunk/MultiChannelUSB/histogram.v
r27 r45 4 4 input wire data_ready, 5 5 input wire [11:0] data, address, 6 output wire [ 31:0] q6 output wire [23:0] q 7 7 ); 8 8 … … 11 11 reg wren_reg, wren_next; 12 12 reg [11:0] addr_reg, addr_next; 13 reg [ 31:0] data_reg, data_next;13 reg [23:0] data_reg, data_next; 14 14 15 wire [ 31:0] q_a_wire, q_b_wire;15 wire [23:0] q_a_wire, q_b_wire; 16 16 17 ram4096x 32 ram4096x32_unit (17 ram4096x24 ram4096x24_unit ( 18 18 .address_a(addr_reg), 19 19 .address_b(address), … … 92 92 // increment and write 93 93 wren_next = 1'b1; 94 data_next = q_a_wire + 32'd1;94 data_next = q_a_wire + 24'd1; 95 95 state_next = 4'd3; 96 96 end … … 104 104 105 105 // output logic 106 assign q =q_b_wire;106 assign q = q_b_wire; 107 107 endmodule -
trunk/MultiChannelUSB/oscilloscope.v
r42 r45 130 130 131 131 // output logic 132 assign q =q_wire;133 assign start_address =trig_reg ? trig_addr_reg ^ 10'h200 : addr_reg + 10'd1;132 assign q = q_wire; 133 assign start_address = trig_reg ? trig_addr_reg ^ 10'h200 : addr_reg + 10'd1; 134 134 135 135 endmodule -
trunk/MultiChannelUSB/usb_fifo.v
r36 r45 24 24 wire [7:0] int_tx_q; 25 25 26 fifo32x8 fifo_tx_unit ( 26 dcfifo #( 27 .intended_device_family("Cyclone III"), 28 .lpm_numwords(16), 29 .lpm_showahead("ON"), 30 .lpm_type("dcfifo"), 31 .lpm_width(8), 32 .lpm_widthu(4), 33 .rdsync_delaypipe(4), 34 .wrsync_delaypipe(4), 35 .overflow_checking("ON"), 36 .underflow_checking("ON"), 37 .use_eab("OFF"), 38 .write_aclr_synch("OFF")) fifo_tx ( 27 39 .aclr(aclr), 28 40 .data(tx_data), … … 33 45 .q(int_tx_q), 34 46 .rdempty(int_tx_empty), 35 .wrfull(tx_full)); 47 .wrfull(tx_full), 48 .rdfull(), 49 .rdusedw(), 50 .wrempty(), 51 .wrusedw()); 36 52 37 fifo32x8 fifo_rx_unit ( 53 dcfifo #( 54 .intended_device_family("Cyclone III"), 55 .lpm_numwords(16), 56 .lpm_showahead("ON"), 57 .lpm_type("dcfifo"), 58 .lpm_width(8), 59 .lpm_widthu(4), 60 .rdsync_delaypipe(4), 61 .wrsync_delaypipe(4), 62 .overflow_checking("ON"), 63 .underflow_checking("ON"), 64 .use_eab("OFF"), 65 .write_aclr_synch("OFF")) fifo_rx ( 38 66 .aclr(aclr), 39 67 .data(int_rx_data), … … 44 72 .q(rx_q), 45 73 .rdempty(rx_empty), 46 .wrfull(int_rx_full)); 74 .wrfull(int_rx_full), 75 .rdfull(), 76 .rdusedw(), 77 .wrempty(), 78 .wrusedw()); 47 79 48 80 assign rx_ready = (~usb_empty) & (~int_rx_full) & (~int_pktend);
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