Changeset 30 for trunk/MultiChannelUSB/Paella.v

Timestamp:

Sep 3, 2009, 2:34:23 PM (15 years ago)

Author:

demin

Message:

put all components in place

File:

• trunk/MultiChannelUSB/Paella.v (modified) (13 diffs)

trunk/MultiChannelUSB/Paella.v

@@ -23 +23 @@
                 input   wire                    USB_FLAGB, // FULL flag for EP8
                 input   wire                    USB_FLAGC,
-                inout   wire    [7:0]   USB_PA,
+                inout   wire                    USB_PA0,
+                inout   wire                    USB_PA1,
+                output  wire                    USB_PA2,
+                inout   wire                    USB_PA3,
+                output  wire                    USB_PA4,
+                output  wire                    USB_PA5,
+                output  wire                    USB_PA6,
+                inout   wire                    USB_PA7,
                 inout   wire    [7:0]   USB_PB,
 
@@ -47 +54 @@
         assign  CON_B           =       16'bz;
         assign  CON_C           =       13'bz;
-        assign  USB_PA          =       {1'bz, ~usb_pktend, usb_addr, 1'bz, ~usb_rden, 2'bz};
+        assign  USB_PA0         =       1'bz;
+        assign  USB_PA1         =       1'bz;
+        assign  USB_PA3         =       1'bz;
+        assign  USB_PA7         =       1'bz;
         assign  RAM_DQAP        =       1'bz;
         assign  RAM_DQA         =       8'bz;
@@ -53 +63 @@
         assign  RAM_DQB         =       8'bz;
 
+
+        assign  USB_PA2         =       ~usb_rden;
+        assign  USB_PA4         =       usb_addr[0];
+        assign  USB_PA5         =       usb_addr[1];
+        assign  USB_PA6         =       ~usb_pktend;
+
         reg             [31:0]  counter;        
-        assign  LED                     =       counter[24];
-//      assign  LED                     =       usb_fifo_led;
+//      assign  LED                     =       counter[24];
+        assign  LED                     =       usb_fifo_rx_empty;
 
         wire                    usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
         wire                    usb_fifo_aclr, usb_fifo_led;
-        wire                    usb_fifo_tx_wrreq, usb_fifo_rx_rdreq;
+        reg                             usb_fifo_tx_wrreq;
+        reg                             usb_fifo_rx_rdreq;
         wire                    usb_fifo_tx_full, usb_fifo_rx_empty;
-        wire    [7:0]   usb_fifo_tx_data, usb_fifo_rx_data;
+        reg             [7:0]   usb_fifo_tx_data;
+        wire    [7:0]   usb_fifo_rx_data;
         wire    [1:0]   usb_addr;
 
@@ -91 +109 @@
         reg             [9:0]   osc_counter;    
         reg                     osc_reset;
-        reg                     osc_bit_num;
+        reg                     osc_byte_num;
         wire    [9:0]   osc_start_addr;
         reg     [9:0]   osc_addr;
@@ -97 +115 @@
 
         reg                     hst_reset;
-        reg     [1:0]   hst_bit_num;
+        reg     [1:0]   hst_byte_num;
         reg     [11:0]  hst_addr;
         wire    [31:0]  hst_q;
 
-        reg             [3:0]   state0, state1, state2;
+        reg             [2:0]   state0, state1, state2;
         reg                             adc_fifo_rdreq;
         wire                    adc_fifo_rdempty;
@@ -149 +167 @@
         );
 
-
+/*
         always @ (posedge adc_clk)
         begin
                 counter <= counter + 32'd1;
         end
+*/
 
         always @ (posedge CLK_50MHz)
@@ -162 +181 @@
                                 if (~adc_fifo_rdempty)
                                 begin
-                                        adc_counter <= adc_counter + 32'd1;
+//                                      adc_counter <= adc_counter + 32'd1;
                                         adc_fifo_rdreq <= 1'b1;
                                         adc_data_ready <= 1'b1;
-                                        state0 <= 4'd2;
+                                        state0 <= 3'd2;
                                 end
                         end
@@ -173 +192 @@
                                 adc_fifo_rdreq <= 1'b0;
                                 adc_data_ready <= 1'b0;
-                                state0 <= 4'd1;
+                                state0 <= 3'd1;
                         end
 
                         default:
                         begin
-                                state0 <= 4'd1;
+                                state0 <= 3'd1;
                         end
                 endcase
         end
 
+        always @(posedge CLK_50MHz)
+        begin
+                case (state1)
+                        1:
+                        begin
+                                usb_fifo_rx_rdreq <= 1'b0;
+                                usb_fifo_tx_wrreq <= 1'b0;
+                                hst_reset <= 1'b0;
+                                osc_reset <= 1'b0;
+                                state1 <= 3'd2;
+                        end
+
+                        2: 
+                        begin
+                                if (~usb_fifo_rx_empty)
+                                begin
+                                        usb_fifo_rx_rdreq <= 1'b1;
+                                        case (usb_fifo_rx_data)
+                                                8'h30:
+                                                begin
+                                                        hst_reset <= 1'b1;
+                                                        state1 <= 3'd1;
+                                                end
+                                                8'h31:
+                                                begin
+                                                        hst_addr <= 12'd0;
+                                                        hst_byte_num <= 2'd0;   
+                                                        state1 <= 3'd3;
+                                                end
+                                                8'h32:
+                                                begin
+                                                        osc_reset <= 1'b1;
+                                                        state1 <= 3'd1;
+                                                end
+                                                8'h33:
+                                                begin
+                                                        osc_addr <= osc_start_addr;
+                                                        osc_counter <= 10'd0;
+                                                        osc_byte_num <= 1'd0;   
+                                                        state1 <= 3'd4;
+                                                end
+                                        endcase
+                                end
+                                else
+                                begin
+                                        usb_fifo_rx_rdreq <= 1'b0;
+                                end                             
+                        end
+
+                        3:
+                        begin
+                                // hst transfer
+                                if (~usb_fifo_tx_full)
+                                begin
+                                        usb_fifo_tx_wrreq <= 1'b1;
+
+                                        case (hst_byte_num)
+                                                2'd0: usb_fifo_tx_data <= hst_q[7:0];
+                                                2'd1: usb_fifo_tx_data <= hst_q[15:8];
+                                                2'd2: usb_fifo_tx_data <= hst_q[23:16];
+                                                2'd3: usb_fifo_tx_data <= hst_q[31:24];
+                                        endcase
+                                        
+                                        if (&hst_byte_num)
+                                        begin
+                                                hst_byte_num <= 2'd0;                           
+                                                if (&hst_addr)
+                                                begin
+                                                        state1 <= 3'd1;
+                                                end
+                                                else
+                                                begin
+                                                        hst_addr <= hst_addr + 12'd1;
+                                                end
+                                        end
+                                        else
+                                        begin
+                                                hst_byte_num <= hst_byte_num + 2'd1;                            
+                                        end                             
+                                end
+                                else
+                                begin
+                                        usb_fifo_tx_wrreq <= 1'b0;
+                                end
+                        end
+
+                        4:
+                        begin
+                                // osc transfer
+                                if(~usb_fifo_tx_full)
+                                begin
+                                        usb_fifo_tx_wrreq <= 1'b1;
+
+                                        case (osc_byte_num)
+                                                1'd0: usb_fifo_tx_data <= osc_q[7:0];
+                                                1'd1: usb_fifo_tx_data <= osc_q[15:8];
+                                        endcase
+        
+                                        if (osc_byte_num)
+                                        begin
+                                                osc_byte_num <= 1'd0;                           
+                                                if (&osc_counter)
+                                                begin
+                                                        state1 <= 3'd1;
+                                                end
+                                                else
+                                                begin
+                                                        osc_addr <= osc_addr + 10'd1;
+                                                        osc_counter <= osc_counter + 10'd1;
+                                                end
+                                        end
+                                        else
+                                        begin
+                                                osc_byte_num <= 1'd1;                           
+                                        end                                                                             
+                                end
+                                else
+                                begin
+                                        usb_fifo_tx_wrreq <= 1'b0;
+                                end
+                        end
+
+                        default:
+                        begin
+                                // default state is the first one
+                                state1 <= 3'd1;
+                        end
+                endcase
+        end
+/*
+        always @(posedge CLK_50MHz)
+        begin
+                case(state1)
+                        0:
+                        begin
+                                usb_fifo_tx_wrreq <= 1'b0;
+                                counter <= 32'd0;
+                                state1 <= 3'd1;
+                        end
+                        1:
+                        begin
+                                if((~usb_fifo_tx_full) & (counter < 32'd512))
+                                begin
+                                        counter <= counter + 32'd1;
+                                        state1 <= 3'd2;
+                                        usb_fifo_tx_data <= 1;
+                                        usb_fifo_tx_wrreq <= 1'b1;
+                                end
+                                else
+                                begin
+                                        usb_fifo_tx_wrreq <= 1'b0;
+                                end
+                        end
+                                
+                        2:
+                        begin
+                                if((~usb_fifo_tx_full) & (counter < 32'd512))
+                                begin
+                                        counter <= counter + 32'd1;
+                                        state1 <= 3'd1;
+                                        usb_fifo_tx_data <= 0;
+                                        usb_fifo_tx_wrreq <= 1'b1;
+                                end
+                                else
+                                begin
+                                        usb_fifo_tx_wrreq <= 1'b0;
+                                end
+                        end
+                                                
+                        default: state1 <= 3'd0;
+                endcase
+        end
+*/
         always @ (posedge adc_clk)
         begin
@@ -189 +381 @@
                         begin
                                 adc_data <= 12'd0;
-                                state2 <= 4'd2;
+                                state2 <= 3'd2;
                         end
                         
@@ -195 +387 @@
                         begin
                                 adc_data <= 12'd1024;
-                                state2 <= 4'd3;
+                                state2 <= 3'd3;
                         end
 
@@ -201 +393 @@
                         begin
                                 adc_data <= 12'd2048;
-                                state2 <= 4'd4;
+                                state2 <= 3'd4;
                         end
 
@@ -207 +399 @@
                         begin
                                 adc_data <= 12'd3072;
-                                state2 <= 4'd5;
+                                state2 <= 3'd5;
                         end
 
@@ -213 +405 @@
                         begin
                                 adc_data <= 12'd4095;
-                                state2 <= 4'd1;
+                                state2 <= 3'd1;
                         end
 
                         default:
                         begin
-                                state2 <= 4'd1;
+                                state2 <= 3'd1;
                         end
                 endcase