source: trunk/MultiChannelUSB/Paella.v@ 30

Last change on this file since 30 was 30, checked in by demin, 15 years ago

put all components in place
File size: 7.9 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
15 input wire ADC_DB,
16 input wire ADC_DC,
17 input wire ADC_DD,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 // Turn output ports off
46 assign RAM_CLK = 1'b0;
47 assign RAM_CE1 = 1'b0;
48 assign RAM_WE = 1'b0;
49 assign RAM_ADDR = 20'h00000;
50
51 // Turn inout ports to tri-state
52 assign TRG = 4'bz;
53 assign CON_A = 7'bz;
54 assign CON_B = 16'bz;
55 assign CON_C = 13'bz;
56 assign USB_PA0 = 1'bz;
57 assign USB_PA1 = 1'bz;
58 assign USB_PA3 = 1'bz;
59 assign USB_PA7 = 1'bz;
60 assign RAM_DQAP = 1'bz;
61 assign RAM_DQA = 8'bz;
62 assign RAM_DQBP = 1'bz;
63 assign RAM_DQB = 8'bz;
64
65
66 assign USB_PA2 = ~usb_rden;
67 assign USB_PA4 = usb_addr[0];
68 assign USB_PA5 = usb_addr[1];
69 assign USB_PA6 = ~usb_pktend;
70
71 reg [31:0] counter;
72// assign LED = counter[24];
73 assign LED = usb_fifo_rx_empty;
74
75 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
76 wire usb_fifo_aclr, usb_fifo_led;
77 reg usb_fifo_tx_wrreq;
78 reg usb_fifo_rx_rdreq;
79 wire usb_fifo_tx_full, usb_fifo_rx_empty;
80 reg [7:0] usb_fifo_tx_data;
81 wire [7:0] usb_fifo_rx_data;
82 wire [1:0] usb_addr;
83
84 assign USB_SLRD = ~usb_rdreq;
85 assign USB_SLWR = ~usb_wrreq;
86
87 usb_fifo usb_fifo_unit
88 (
89 .usb_clk(USB_IFCLK),
90 .usb_data(USB_PB),
91 .usb_full(~USB_FLAGB),
92 .usb_empty(~USB_FLAGA),
93 .usb_wrreq(usb_wrreq),
94 .usb_rdreq(usb_rdreq),
95 .usb_rden(usb_rden),
96 .usb_pktend(usb_pktend),
97 .usb_addr(usb_addr),
98 .clk(CLK_50MHz),
99 .aclr(usb_fifo_aclr),
100 .tx_wrreq(usb_fifo_tx_wrreq),
101 .rx_rdreq(usb_fifo_rx_rdreq),
102 .tx_data(usb_fifo_tx_data),
103 .tx_full(usb_fifo_tx_full),
104 .rx_empty(usb_fifo_rx_empty),
105// .led(usb_fifo_led),
106 .rx_data(usb_fifo_rx_data)
107 );
108
109 reg [9:0] osc_counter;
110 reg osc_reset;
111 reg osc_byte_num;
112 wire [9:0] osc_start_addr;
113 reg [9:0] osc_addr;
114 wire [15:0] osc_q;
115
116 reg hst_reset;
117 reg [1:0] hst_byte_num;
118 reg [11:0] hst_addr;
119 wire [31:0] hst_q;
120
121 reg [2:0] state0, state1, state2;
122 reg adc_fifo_rdreq;
123 wire adc_fifo_rdempty;
124 reg adc_fifo_aclr;
125
126 reg [31:0] adc_counter;
127 reg adc_data_ready;
128 wire adc_clk;
129 reg [11:0] adc_data;
130 wire [11:0] raw_data;
131 wire [11:0] uwt_data;
132 wire [1:0] uwt_flag;
133
134 pll pll_unit(
135 .inclk0(CLK_50MHz),
136 .c0(adc_clk));
137
138 adc_fifo adc_fifo_unit (
139 .adc_clk(adc_clk),
140 .adc_data(adc_data),
141 .aclr(adc_fifo_aclr),
142 .rdclk(CLK_50MHz),
143 .rdreq(adc_fifo_rdreq),
144 .rdempty(adc_fifo_rdempty),
145 .raw_data(raw_data),
146 .uwt_data({uwt_flag, uwt_data}));
147
148 histogram histogram_unit (
149 .clk(CLK_50MHz),
150 .reset(hst_reset),
151 .data_ready(adc_data_ready),
152 .data(raw_data),
153 .address(hst_addr),
154 .q(hst_q)
155 );
156
157 oscilloscope oscilloscope_unit (
158 .clk(CLK_50MHz),
159 .reset(osc_reset),
160 .data_ready(adc_data_ready),
161 .raw_data(raw_data),
162 .uwt_data(uwt_data),
163 .threshold(16'd100),
164 .address(osc_addr),
165 .start_address(osc_start_addr),
166 .q(osc_q)
167 );
168
169/*
170 always @ (posedge adc_clk)
171 begin
172 counter <= counter + 32'd1;
173 end
174*/
175
176 always @ (posedge CLK_50MHz)
177 begin
178 case (state0)
179 1:
180 begin
181 if (~adc_fifo_rdempty)
182 begin
183// adc_counter <= adc_counter + 32'd1;
184 adc_fifo_rdreq <= 1'b1;
185 adc_data_ready <= 1'b1;
186 state0 <= 3'd2;
187 end
188 end
189
190 2:
191 begin
192 adc_fifo_rdreq <= 1'b0;
193 adc_data_ready <= 1'b0;
194 state0 <= 3'd1;
195 end
196
197 default:
198 begin
199 state0 <= 3'd1;
200 end
201 endcase
202 end
203
204 always @(posedge CLK_50MHz)
205 begin
206 case (state1)
207 1:
208 begin
209 usb_fifo_rx_rdreq <= 1'b0;
210 usb_fifo_tx_wrreq <= 1'b0;
211 hst_reset <= 1'b0;
212 osc_reset <= 1'b0;
213 state1 <= 3'd2;
214 end
215
216 2:
217 begin
218 if (~usb_fifo_rx_empty)
219 begin
220 usb_fifo_rx_rdreq <= 1'b1;
221 case (usb_fifo_rx_data)
222 8'h30:
223 begin
224 hst_reset <= 1'b1;
225 state1 <= 3'd1;
226 end
227 8'h31:
228 begin
229 hst_addr <= 12'd0;
230 hst_byte_num <= 2'd0;
231 state1 <= 3'd3;
232 end
233 8'h32:
234 begin
235 osc_reset <= 1'b1;
236 state1 <= 3'd1;
237 end
238 8'h33:
239 begin
240 osc_addr <= osc_start_addr;
241 osc_counter <= 10'd0;
242 osc_byte_num <= 1'd0;
243 state1 <= 3'd4;
244 end
245 endcase
246 end
247 else
248 begin
249 usb_fifo_rx_rdreq <= 1'b0;
250 end
251 end
252
253 3:
254 begin
255 // hst transfer
256 if (~usb_fifo_tx_full)
257 begin
258 usb_fifo_tx_wrreq <= 1'b1;
259
260 case (hst_byte_num)
261 2'd0: usb_fifo_tx_data <= hst_q[7:0];
262 2'd1: usb_fifo_tx_data <= hst_q[15:8];
263 2'd2: usb_fifo_tx_data <= hst_q[23:16];
264 2'd3: usb_fifo_tx_data <= hst_q[31:24];
265 endcase
266
267 if (&hst_byte_num)
268 begin
269 hst_byte_num <= 2'd0;
270 if (&hst_addr)
271 begin
272 state1 <= 3'd1;
273 end
274 else
275 begin
276 hst_addr <= hst_addr + 12'd1;
277 end
278 end
279 else
280 begin
281 hst_byte_num <= hst_byte_num + 2'd1;
282 end
283 end
284 else
285 begin
286 usb_fifo_tx_wrreq <= 1'b0;
287 end
288 end
289
290 4:
291 begin
292 // osc transfer
293 if(~usb_fifo_tx_full)
294 begin
295 usb_fifo_tx_wrreq <= 1'b1;
296
297 case (osc_byte_num)
298 1'd0: usb_fifo_tx_data <= osc_q[7:0];
299 1'd1: usb_fifo_tx_data <= osc_q[15:8];
300 endcase
301
302 if (osc_byte_num)
303 begin
304 osc_byte_num <= 1'd0;
305 if (&osc_counter)
306 begin
307 state1 <= 3'd1;
308 end
309 else
310 begin
311 osc_addr <= osc_addr + 10'd1;
312 osc_counter <= osc_counter + 10'd1;
313 end
314 end
315 else
316 begin
317 osc_byte_num <= 1'd1;
318 end
319 end
320 else
321 begin
322 usb_fifo_tx_wrreq <= 1'b0;
323 end
324 end
325
326 default:
327 begin
328 // default state is the first one
329 state1 <= 3'd1;
330 end
331 endcase
332 end
333/*
334 always @(posedge CLK_50MHz)
335 begin
336 case(state1)
337 0:
338 begin
339 usb_fifo_tx_wrreq <= 1'b0;
340 counter <= 32'd0;
341 state1 <= 3'd1;
342 end
343 1:
344 begin
345 if((~usb_fifo_tx_full) & (counter < 32'd512))
346 begin
347 counter <= counter + 32'd1;
348 state1 <= 3'd2;
349 usb_fifo_tx_data <= 1;
350 usb_fifo_tx_wrreq <= 1'b1;
351 end
352 else
353 begin
354 usb_fifo_tx_wrreq <= 1'b0;
355 end
356 end
357
358 2:
359 begin
360 if((~usb_fifo_tx_full) & (counter < 32'd512))
361 begin
362 counter <= counter + 32'd1;
363 state1 <= 3'd1;
364 usb_fifo_tx_data <= 0;
365 usb_fifo_tx_wrreq <= 1'b1;
366 end
367 else
368 begin
369 usb_fifo_tx_wrreq <= 1'b0;
370 end
371 end
372
373 default: state1 <= 3'd0;
374 endcase
375 end
376*/
377 always @ (posedge adc_clk)
378 begin
379 case (state2)
380 1:
381 begin
382 adc_data <= 12'd0;
383 state2 <= 3'd2;
384 end
385
386 2:
387 begin
388 adc_data <= 12'd1024;
389 state2 <= 3'd3;
390 end
391
392 3:
393 begin
394 adc_data <= 12'd2048;
395 state2 <= 3'd4;
396 end
397
398 4:
399 begin
400 adc_data <= 12'd3072;
401 state2 <= 3'd5;
402 end
403
404 5:
405 begin
406 adc_data <= 12'd4095;
407 state2 <= 3'd1;
408 end
409
410 default:
411 begin
412 state2 <= 3'd1;
413 end
414 endcase
415 end
416
417endmodule
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