source: trunk/MultiChannelUSB/Paella.v@ 113

Last change on this file since 113 was 101, checked in by demin, 16 years ago

add exposure counter
File size: 10.2 KB
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[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
[68]7 inout wire I2C_SDA,
[72]8 inout wire I2C_SCL,
[68]9 inout wire [4:0] CON_A,
[84]10 input wire [15:0] CON_B,
[63]11 input wire [12:0] CON_C,
[27]12 input wire [1:0] CON_BCLK,
13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
[41]17 input wire [2:0] ADC_D,
[27]18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
[30]25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
[27]33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
[72]45 localparam N = 3;
46
[27]47 // Turn output ports off
[65]48/*
[27]49 assign RAM_CLK = 1'b0;
50 assign RAM_CE1 = 1'b0;
51 assign RAM_WE = 1'b0;
52 assign RAM_ADDR = 20'h00000;
[65]53*/
[90]54 assign RAM_CLK = sys_clock;
[65]55 assign RAM_CE1 = 1'b0;
[27]56
57 // Turn inout ports to tri-state
58 assign TRG = 4'bz;
[68]59 assign CON_A = 5'bz;
[30]60 assign USB_PA0 = 1'bz;
61 assign USB_PA1 = 1'bz;
62 assign USB_PA3 = 1'bz;
63 assign USB_PA7 = 1'bz;
[65]64// assign RAM_DQAP = 1'bz;
65// assign RAM_DQA = 8'bz;
66// assign RAM_DQBP = 1'bz;
67// assign RAM_DQB = 8'bz;
[27]68
[30]69 assign USB_PA2 = ~usb_rden;
70 assign USB_PA4 = usb_addr[0];
71 assign USB_PA5 = usb_addr[1];
72 assign USB_PA6 = ~usb_pktend;
73
[27]74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[59]75 wire usb_tx_wrreq, usb_rx_rdreq;
76 wire usb_tx_full, usb_rx_empty;
77 wire [7:0] usb_tx_data, usb_rx_data;
[27]78 wire [1:0] usb_addr;
79
80 assign USB_SLRD = ~usb_rdreq;
81 assign USB_SLWR = ~usb_wrreq;
82
[59]83 usb_fifo usb_unit
[27]84 (
85 .usb_clk(USB_IFCLK),
86 .usb_data(USB_PB),
87 .usb_full(~USB_FLAGB),
88 .usb_empty(~USB_FLAGA),
89 .usb_wrreq(usb_wrreq),
90 .usb_rdreq(usb_rdreq),
91 .usb_rden(usb_rden),
92 .usb_pktend(usb_pktend),
93 .usb_addr(usb_addr),
[34]94
[90]95 .clk(sys_clock),
[34]96
[59]97 .tx_full(usb_tx_full),
98 .tx_wrreq(usb_tx_wrreq),
99 .tx_data(usb_tx_data),
[34]100
[59]101 .rx_empty(usb_rx_empty),
102 .rx_rdreq(usb_rx_rdreq),
103 .rx_q(usb_rx_data)
[27]104 );
[84]105
[101]106 wire ana_dead [N-1:0];
[90]107 wire ana_good [N-1:0];
108 wire [11:0] ana_data [N-1:0];
109 wire [11:0] ana_base [N-1:0];
[44]110
[101]111 wire cnt_good [N-1:0];
112
[72]113 wire [11:0] osc_mux_data [N-1:0];
114
[90]115 wire [11:0] trg_mux_data;
116 wire trg_flag;
[72]117
[90]118 wire [83:0] int_mux_data [N-1:0];
[72]119
[90]120 wire sys_clock, sys_frame;
[72]121
122 wire [11:0] adc_data [N-1:0];
123 wire [11:0] int_data [N-1:0];
[101]124 wire [11:0] sys_data [N-1:0];
[84]125 wire [11:0] cmp_data;
126 wire [11:0] nowhere;
127
[72]128 wire [31:0] uwt_d1 [N-1:0];
129 wire [31:0] uwt_a1 [N-1:0];
130 wire [31:0] uwt_peak1 [N-1:0];
131 wire [31:0] uwt_d2 [N-1:0];
132 wire [31:0] uwt_a2 [N-1:0];
133 wire [31:0] uwt_peak2 [N-1:0];
134 wire [31:0] uwt_d3 [N-1:0];
135 wire [31:0] uwt_a3 [N-1:0];
136 wire [31:0] uwt_peak3 [N-1:0];
[63]137
[72]138 wire [1:0] uwt_flag1 [N-1:0];
139 wire [1:0] uwt_flag2 [N-1:0];
140 wire [1:0] uwt_flag3 [N-1:0];
[90]141
142 wire i2c_reset;
[63]143
[68]144/*
[63]145 adc_para adc_para_unit (
146 .lvds_dco(ADC_DCO),
147 .lvds_fco(ADC_FCO),
[90]148 .para_good(CON_CCLK[0]),
[63]149 .para_data(CON_C[11:0]),
[81]150 .adc_data(adc_data[2]));
[68]151*/
[101]152
[54]153 wire adc_pll_clk;
154
[101]155/*
[54]156 adc_pll adc_pll_unit(
157 .inclk0(ADC_FCO),
158 .c0(adc_pll_clk));
159*/
[48]160
[101]161 sys_pll sys_pll_unit(
162 .inclk0(CLK_50MHz),
163 .c0(sys_clock));
164
[59]165 test test_unit(
[84]166 .clk(ADC_FCO),
[101]167 .data(adc_data[2]));
168// .data(nowhere));
[48]169
[63]170 adc_lvds #(
[81]171 .size(3),
[63]172 .width(12)) adc_lvds_unit (
[41]173 .lvds_dco(ADC_DCO),
[54]174// .lvds_dco(adc_pll_clk),
[41]175 .lvds_fco(ADC_FCO),
[81]176 .lvds_d(ADC_D[2:0]),
[101]177// .adc_data({ adc_data[2],
178 .adc_data({ nowhere,
[81]179 adc_data[1],
[72]180 adc_data[0] }));
[101]181
182/*
[90]183 assign cmp_data = CON_B[11:0];
184 assign sys_clock = ADC_DCO;
185 assign sys_frame = ADC_FCO;
[101]186*/
[72]187
[101]188 wire [15:0] cfg_bits [31:0];
189 wire [511:0] int_cfg_bits;
[72]190
[90]191 wire [31:0] cfg_mux_selector;
[72]192
193 wire cfg_reset;
194
[101]195 wire [8:0] bus_ssel;
[90]196 wire bus_wren;
197 wire [31:0] bus_addr;
198 wire [15:0] bus_mosi;
[101]199 wire [15:0] bus_miso [7:0];
200 wire [8:0] bus_busy;
[72]201
[90]202 wire [15:0] mrg_bus_miso;
203 wire mrg_bus_busy;
[72]204
[101]205 wire [127:0] int_bus_miso;
[84]206
[90]207 genvar j;
[72]208
[44]209 generate
[101]210 for (j = 0; j < 32; j = j + 1)
[90]211 begin : CONFIGURATION_OUTPUT
212 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
213 end
214 endgenerate
[72]215
[90]216 configuration configuration_unit (
217 .clock(sys_clock),
218 .reset(cfg_reset),
219 .bus_ssel(bus_ssel[0]),
220 .bus_wren(bus_wren),
[101]221 .bus_addr(bus_addr[4:0]),
[90]222 .bus_mosi(bus_mosi),
223 .bus_miso(bus_miso[0]),
224 .bus_busy(bus_busy[0]),
225 .cfg_bits(int_cfg_bits));
[72]226
[90]227 generate
228 for (j = 0; j < 3; j = j + 1)
229 begin : MUX_DATA
230 assign int_mux_data[j] = {
231 {ana_good[j], 11'd0},
232 ana_data[j],
233 ana_base[j],
234 uwt_a3[j][20:9],
235 uwt_a2[j][17:6],
236 uwt_a1[j][14:3],
[101]237 sys_data[j]};
[90]238 end
239 endgenerate
[72]240
[101]241 assign cfg_mux_selector = {cfg_bits[3], cfg_bits[2]};
[75]242
[90]243 lpm_mux #(
244 .lpm_size(21),
245 .lpm_type("LPM_MUX"),
246 .lpm_width(12),
247 .lpm_widths(5)) trg_mux_unit (
248 .sel(cfg_mux_selector[28:24]),
249 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
250 .result(trg_mux_data));
[72]251
[90]252 generate
253 for (j = 0; j < 3; j = j + 1)
254 begin : OSC_CHAIN
[72]255
256 lpm_mux #(
[90]257 .lpm_size(21),
[72]258 .lpm_type("LPM_MUX"),
259 .lpm_width(12),
[90]260 .lpm_widths(5)) osc_mux_unit (
261 .sel(cfg_mux_selector[j*8+4:j*8]),
262 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
263 .result(osc_mux_data[j]));
264
265 end
266 endgenerate
[72]267
[90]268 trigger trigger_unit (
269 .clock(sys_clock),
270 .frame(sys_frame),
[101]271 .reset(cfg_bits[0][0]),
272 .cfg_data(cfg_bits[5][11:0]),
[90]273 .trg_data(trg_mux_data),
274 .trg_flag(trg_flag));
[27]275
[90]276 oscilloscope oscilloscope_unit (
277 .clock(sys_clock),
278 .frame(sys_frame),
[101]279 .reset(cfg_bits[0][1]),
280 .cfg_data(cfg_bits[4][0]),
[90]281 .trg_flag(trg_flag),
282 .osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
283 .ram_wren(RAM_WE),
284 .ram_addr(RAM_ADDR),
285 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
286 .bus_ssel(bus_ssel[1]),
287 .bus_wren(bus_wren),
288 .bus_addr(bus_addr[19:0]),
289 .bus_mosi(bus_mosi),
290 .bus_miso(bus_miso[1]),
291 .bus_busy(bus_busy[1]));
[72]292
[101]293
294 adc_fifo #(.W(48)) adc_fifo_unit (
295 .adc_clock(ADC_FCO),
296 .adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}),
297 .sys_clock(sys_clock),
298 .sys_frame(sys_frame),
299 .sys_data({cmp_data, int_data[2], int_data[1], int_data[0]}));
300
301
[90]302 generate
303 for (j = 0; j < 3; j = j + 1)
304 begin : MCA_CHAIN
[72]305
[101]306 assign sys_data[j] = (cfg_bits[1][4*j]) ? (int_data[j] ^ 12'hfff) : (int_data[j]);
[90]307
308 uwt_bior31 #(.L(1)) uwt_1_unit (
309 .clock(sys_clock),
310 .frame(sys_frame),
311 .reset(1'b0),
[101]312 .x({20'h00000, sys_data[j]}),
[90]313 .d(uwt_d1[j]),
314 .a(uwt_a1[j]),
315 .peak(uwt_peak1[j]),
316 .flag(uwt_flag1[j]));
317
318 uwt_bior31 #(.L(2)) uwt_2_unit (
319 .clock(sys_clock),
320 .frame(sys_frame),
321 .reset(1'b0),
322 .x(uwt_a1[j]),
323 .d(uwt_d2[j]),
324 .a(uwt_a2[j]),
325 .peak(uwt_peak2[j]),
326 .flag(uwt_flag2[j]));
327
328 uwt_bior31 #(.L(3)) uwt_3_unit (
329 .clock(sys_clock),
330 .frame(sys_frame),
331 .reset(1'b0),
332 .x(uwt_a2[j]),
333 .d(uwt_d3[j]),
334 .a(uwt_a3[j]),
335 .peak(uwt_peak3[j]),
336 .flag(uwt_flag3[j]));
337
[44]338 analyser analyser_unit (
[90]339 .clock(sys_clock),
340 .frame(sys_frame),
[101]341 .reset(cfg_bits[0][2+j]),
342 .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
[90]343 .uwt_flag(uwt_flag3[j]),
344 .uwt_data(uwt_peak3[j]),
[101]345 .ana_dead(ana_dead[j]),
[90]346 .ana_good(ana_good[j]),
347 .ana_data(ana_data[j]),
348 .ana_base(ana_base[j]));
[54]349
[90]350 histogram histogram_unit (
351 .clock(sys_clock),
352 .frame(sys_frame),
[101]353 .reset(cfg_bits[0][5+j]),
354 .hst_good((ana_good[j]) & (cnt_good[j])),
[90]355 .hst_data(ana_data[j]),
356 .bus_ssel(bus_ssel[2+j]),
357 .bus_wren(bus_wren),
358 .bus_addr(bus_addr[12:0]),
359 .bus_mosi(bus_mosi),
360 .bus_miso(bus_miso[2+j]),
361 .bus_busy(bus_busy[2+j]));
[84]362
[101]363 counter counter_unit (
364 .clock(sys_clock),
365 .frame((sys_frame) & (~ana_dead[j])),
366 .reset(cfg_bits[0][8+j]),
367 .cfg_data(cfg_bits[12+j]),
368 .bus_ssel(bus_ssel[5+j]),
369 .bus_wren(bus_wren),
370 .bus_addr(bus_addr[1:0]),
371 .bus_mosi(bus_mosi),
372 .bus_miso(bus_miso[5+j]),
373 .bus_busy(bus_busy[5+j]),
374 .cnt_good(cnt_good[j]));
375
[44]376 end
377 endgenerate
[27]378
[68]379 i2c_fifo i2c_unit(
[90]380 .clock(sys_clock),
381 .reset(i2c_reset),
[70]382/*
383 normal connection
[68]384 .i2c_sda(I2C_SDA),
[70]385 .i2c_scl(I2C_SCL),
[68]386
[70]387 following is a cross wire connection for EPT
388*/
389 .i2c_sda(I2C_SCL),
[90]390 .i2c_scl(I2C_SDA),
391
[101]392 .bus_ssel(bus_ssel[8]),
[90]393 .bus_wren(bus_wren),
394 .bus_mosi(bus_mosi),
[101]395 .bus_busy(bus_busy[8]));
[70]396
[90]397 generate
[101]398 for (j = 0; j < 8; j = j + 1)
[90]399 begin : BUS_OUTPUT
400 assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
401 end
402 endgenerate
403
404 lpm_mux #(
[101]405 .lpm_size(8),
[90]406 .lpm_type("LPM_MUX"),
407 .lpm_width(16),
408 .lpm_widths(3)) bus_miso_mux_unit (
409 .sel(bus_addr[30:28]),
410 .data(int_bus_miso),
411 .result(mrg_bus_miso));
412
413 lpm_mux #(
[101]414 .lpm_size(9),
[90]415 .lpm_type("LPM_MUX"),
416 .lpm_width(1),
[101]417 .lpm_widths(4)) bus_busy_mux_unit (
418 .sel(bus_addr[31:28]),
[90]419 .data(bus_busy),
420 .result(mrg_bus_busy));
421
422/*
423 lpm_or #(
424 .lpm_size(6),
425 .lpm_type("LPM_OR"),
426 .lpm_width(16)) bus_miso_or_unit (
427 .data(int_bus_miso),
428 .result(mrg_bus_miso));
429*/
430
431 lpm_decode #(
[101]432 .lpm_decodes(9),
[90]433 .lpm_type("LPM_DECODE"),
[101]434 .lpm_width(4)) lpm_decode_unit (
435 .data(bus_addr[31:28]),
[90]436 .eq(bus_ssel),
437 .aclr(),
438 .clken(),
439 .clock(),
440 .enable());
441
[59]442 control control_unit (
[90]443 .clock(sys_clock),
[59]444 .rx_empty(usb_rx_empty),
445 .tx_full(usb_tx_full),
446 .rx_data(usb_rx_data),
447 .rx_rdreq(usb_rx_rdreq),
448 .tx_wrreq(usb_tx_wrreq),
449 .tx_data(usb_tx_data),
[90]450 .bus_wren(bus_wren),
451 .bus_addr(bus_addr),
452 .bus_mosi(bus_mosi),
453 .bus_miso(mrg_bus_miso),
454 .bus_busy(mrg_bus_busy),
[59]455 .led(LED));
[45]456
[84]457/*
458 altserial_flash_loader #(
459 .enable_shared_access("OFF"),
460 .enhanced_mode(1),
461 .intended_device_family("Cyclone III")) sfl_unit (
462 .noe(1'b0),
463 .asmi_access_granted(),
464 .asmi_access_request(),
465 .data0out(),
466 .dclkin(),
467 .scein(),
468 .sdoin());
469*/
470
[54]471endmodule
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