[27] | 1 | module Paella
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| 2 | (
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| 3 | input wire CLK_50MHz,
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| 4 | output wire LED,
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| 5 |
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| 6 | inout wire [3:0] TRG,
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[68] | 7 | inout wire I2C_SDA,
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[72] | 8 | inout wire I2C_SCL,
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[68] | 9 | inout wire [4:0] CON_A,
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[84] | 10 | input wire [15:0] CON_B,
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[63] | 11 | input wire [12:0] CON_C,
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[27] | 12 | input wire [1:0] CON_BCLK,
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| 13 | input wire [1:0] CON_CCLK,
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| 14 |
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| 15 | input wire ADC_DCO,
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| 16 | input wire ADC_FCO,
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[41] | 17 | input wire [2:0] ADC_D,
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[27] | 18 |
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| 19 | output wire USB_SLRD,
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| 20 | output wire USB_SLWR,
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| 21 | input wire USB_IFCLK,
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| 22 | input wire USB_FLAGA, // EMPTY flag for EP6
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| 23 | input wire USB_FLAGB, // FULL flag for EP8
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| 24 | input wire USB_FLAGC,
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[30] | 25 | inout wire USB_PA0,
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| 26 | inout wire USB_PA1,
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| 27 | output wire USB_PA2,
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| 28 | inout wire USB_PA3,
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| 29 | output wire USB_PA4,
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| 30 | output wire USB_PA5,
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| 31 | output wire USB_PA6,
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| 32 | inout wire USB_PA7,
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[27] | 33 | inout wire [7:0] USB_PB,
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| 34 |
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| 35 | output wire RAM_CLK,
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| 36 | output wire RAM_CE1,
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| 37 | output wire RAM_WE,
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| 38 | output wire [19:0] RAM_ADDR,
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| 39 | inout wire RAM_DQAP,
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| 40 | inout wire [7:0] RAM_DQA,
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| 41 | inout wire RAM_DQBP,
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| 42 | inout wire [7:0] RAM_DQB
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| 43 | );
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| 44 |
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[72] | 45 | localparam N = 3;
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| 46 |
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[27] | 47 | // Turn output ports off
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[65] | 48 | /*
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[27] | 49 | assign RAM_CLK = 1'b0;
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| 50 | assign RAM_CE1 = 1'b0;
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| 51 | assign RAM_WE = 1'b0;
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| 52 | assign RAM_ADDR = 20'h00000;
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[65] | 53 | */
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[90] | 54 | assign RAM_CLK = sys_clock;
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[65] | 55 | assign RAM_CE1 = 1'b0;
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[27] | 56 |
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| 57 | // Turn inout ports to tri-state
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| 58 | assign TRG = 4'bz;
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[68] | 59 | assign CON_A = 5'bz;
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[30] | 60 | assign USB_PA0 = 1'bz;
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| 61 | assign USB_PA1 = 1'bz;
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| 62 | assign USB_PA3 = 1'bz;
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| 63 | assign USB_PA7 = 1'bz;
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[65] | 64 | // assign RAM_DQAP = 1'bz;
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| 65 | // assign RAM_DQA = 8'bz;
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| 66 | // assign RAM_DQBP = 1'bz;
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| 67 | // assign RAM_DQB = 8'bz;
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[27] | 68 |
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[30] | 69 | assign USB_PA2 = ~usb_rden;
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| 70 | assign USB_PA4 = usb_addr[0];
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| 71 | assign USB_PA5 = usb_addr[1];
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| 72 | assign USB_PA6 = ~usb_pktend;
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| 73 |
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[27] | 74 | wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
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[59] | 75 | wire usb_tx_wrreq, usb_rx_rdreq;
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| 76 | wire usb_tx_full, usb_rx_empty;
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| 77 | wire [7:0] usb_tx_data, usb_rx_data;
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[27] | 78 | wire [1:0] usb_addr;
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| 79 |
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| 80 | assign USB_SLRD = ~usb_rdreq;
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| 81 | assign USB_SLWR = ~usb_wrreq;
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| 82 |
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[59] | 83 | usb_fifo usb_unit
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[27] | 84 | (
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| 85 | .usb_clk(USB_IFCLK),
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| 86 | .usb_data(USB_PB),
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| 87 | .usb_full(~USB_FLAGB),
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| 88 | .usb_empty(~USB_FLAGA),
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| 89 | .usb_wrreq(usb_wrreq),
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| 90 | .usb_rdreq(usb_rdreq),
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| 91 | .usb_rden(usb_rden),
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| 92 | .usb_pktend(usb_pktend),
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| 93 | .usb_addr(usb_addr),
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[34] | 94 |
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[90] | 95 | .clk(sys_clock),
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[34] | 96 |
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[59] | 97 | .tx_full(usb_tx_full),
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| 98 | .tx_wrreq(usb_tx_wrreq),
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| 99 | .tx_data(usb_tx_data),
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[34] | 100 |
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[59] | 101 | .rx_empty(usb_rx_empty),
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| 102 | .rx_rdreq(usb_rx_rdreq),
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| 103 | .rx_q(usb_rx_data)
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[27] | 104 | );
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[84] | 105 |
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[90] | 106 | wire ana_good [N-1:0];
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| 107 | wire [11:0] ana_data [N-1:0];
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| 108 | wire [11:0] ana_base [N-1:0];
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[44] | 109 |
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[72] | 110 | wire [11:0] osc_mux_data [N-1:0];
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| 111 |
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[90] | 112 | wire [11:0] trg_mux_data;
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| 113 | wire trg_flag;
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[72] | 114 |
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[90] | 115 | wire [83:0] int_mux_data [N-1:0];
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[72] | 116 |
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[90] | 117 | wire sys_clock, sys_frame;
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[72] | 118 |
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| 119 | wire [11:0] adc_data [N-1:0];
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| 120 | wire [11:0] int_data [N-1:0];
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[84] | 121 | wire [11:0] cmp_data;
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| 122 | wire [11:0] nowhere;
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| 123 |
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[72] | 124 | wire [31:0] uwt_d1 [N-1:0];
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| 125 | wire [31:0] uwt_a1 [N-1:0];
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| 126 | wire [31:0] uwt_peak1 [N-1:0];
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| 127 | wire [31:0] uwt_d2 [N-1:0];
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| 128 | wire [31:0] uwt_a2 [N-1:0];
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| 129 | wire [31:0] uwt_peak2 [N-1:0];
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| 130 | wire [31:0] uwt_d3 [N-1:0];
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| 131 | wire [31:0] uwt_a3 [N-1:0];
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| 132 | wire [31:0] uwt_peak3 [N-1:0];
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[63] | 133 |
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[72] | 134 | wire [1:0] uwt_flag1 [N-1:0];
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| 135 | wire [1:0] uwt_flag2 [N-1:0];
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| 136 | wire [1:0] uwt_flag3 [N-1:0];
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[90] | 137 |
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| 138 | wire i2c_reset;
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[63] | 139 |
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[68] | 140 | /*
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[63] | 141 | adc_para adc_para_unit (
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| 142 | .lvds_dco(ADC_DCO),
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| 143 | .lvds_fco(ADC_FCO),
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[90] | 144 | .para_good(CON_CCLK[0]),
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[63] | 145 | .para_data(CON_C[11:0]),
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[81] | 146 | .adc_data(adc_data[2]));
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[68] | 147 | */
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[59] | 148 | /*
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[54] | 149 | wire adc_pll_clk;
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| 150 |
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| 151 | adc_pll adc_pll_unit(
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| 152 | .inclk0(ADC_FCO),
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| 153 | .c0(adc_pll_clk));
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| 154 | */
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[48] | 155 |
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[59] | 156 | test test_unit(
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[84] | 157 | .clk(ADC_FCO),
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[90] | 158 | // .data(adc_data[2]));
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| 159 | .data(nowhere));
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[48] | 160 |
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[63] | 161 | adc_lvds #(
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[81] | 162 | .size(3),
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[63] | 163 | .width(12)) adc_lvds_unit (
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[41] | 164 | .lvds_dco(ADC_DCO),
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[54] | 165 | // .lvds_dco(adc_pll_clk),
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[41] | 166 | .lvds_fco(ADC_FCO),
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[81] | 167 | .lvds_d(ADC_D[2:0]),
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[90] | 168 | .adc_data({ adc_data[2],
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| 169 | // .adc_data({ nowhere,
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[81] | 170 | adc_data[1],
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[72] | 171 | adc_data[0] }));
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[90] | 172 |
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| 173 | assign cmp_data = CON_B[11:0];
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| 174 | assign sys_clock = ADC_DCO;
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| 175 | assign sys_frame = ADC_FCO;
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[72] | 176 |
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[90] | 177 | wire [15:0] cfg_bits [15:0];
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| 178 | wire [255:0] int_cfg_bits;
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[72] | 179 |
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[90] | 180 | wire [31:0] cfg_mux_selector;
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[72] | 181 |
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| 182 | wire cfg_reset;
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| 183 |
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[90] | 184 | wire [7:0] bus_ssel;
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| 185 | wire bus_wren;
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| 186 | wire [31:0] bus_addr;
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| 187 | wire [15:0] bus_mosi;
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| 188 | wire [15:0] bus_miso [5:0];
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| 189 | wire [5:0] bus_busy;
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[72] | 190 |
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[90] | 191 | wire [15:0] mrg_bus_miso;
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| 192 | wire mrg_bus_busy;
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[72] | 193 |
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[90] | 194 | wire [79:0] int_bus_miso;
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[84] | 195 |
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[90] | 196 | genvar j;
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[72] | 197 |
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[44] | 198 | generate
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[90] | 199 | for (j = 0; j < 16; j = j + 1)
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| 200 | begin : CONFIGURATION_OUTPUT
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| 201 | assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
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| 202 | end
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| 203 | endgenerate
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[72] | 204 |
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[90] | 205 | configuration configuration_unit (
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| 206 | .clock(sys_clock),
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| 207 | .reset(cfg_reset),
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| 208 | .bus_ssel(bus_ssel[0]),
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| 209 | .bus_wren(bus_wren),
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| 210 | .bus_addr(bus_addr[3:0]),
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| 211 | .bus_mosi(bus_mosi),
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| 212 | .bus_miso(bus_miso[0]),
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| 213 | .bus_busy(bus_busy[0]),
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| 214 | .cfg_bits(int_cfg_bits));
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[72] | 215 |
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[90] | 216 | generate
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| 217 | for (j = 0; j < 3; j = j + 1)
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| 218 | begin : MUX_DATA
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| 219 | assign int_mux_data[j] = {
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| 220 | {ana_good[j], 11'd0},
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| 221 | ana_data[j],
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| 222 | ana_base[j],
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| 223 | uwt_a3[j][20:9],
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| 224 | uwt_a2[j][17:6],
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| 225 | uwt_a1[j][14:3],
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| 226 | adc_data[j]};
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| 227 | end
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| 228 | endgenerate
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[72] | 229 |
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[90] | 230 | assign cfg_mux_selector = {cfg_bits[11], cfg_bits[10]};
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[75] | 231 |
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[90] | 232 | lpm_mux #(
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| 233 | .lpm_size(21),
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| 234 | .lpm_type("LPM_MUX"),
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| 235 | .lpm_width(12),
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| 236 | .lpm_widths(5)) trg_mux_unit (
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| 237 | .sel(cfg_mux_selector[28:24]),
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| 238 | .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
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| 239 | .result(trg_mux_data));
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[72] | 240 |
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[90] | 241 | generate
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| 242 | for (j = 0; j < 3; j = j + 1)
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| 243 | begin : OSC_CHAIN
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[72] | 244 |
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| 245 | lpm_mux #(
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[90] | 246 | .lpm_size(21),
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[72] | 247 | .lpm_type("LPM_MUX"),
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| 248 | .lpm_width(12),
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[90] | 249 | .lpm_widths(5)) osc_mux_unit (
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| 250 | .sel(cfg_mux_selector[j*8+4:j*8]),
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| 251 | .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
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| 252 | .result(osc_mux_data[j]));
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| 253 |
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| 254 | end
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| 255 | endgenerate
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[72] | 256 |
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[90] | 257 | trigger trigger_unit (
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| 258 | .clock(sys_clock),
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| 259 | .frame(sys_frame),
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| 260 | .reset(cfg_bits[12][14]),
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| 261 | .cfg_data(cfg_bits[12][11:0]),
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| 262 | .trg_data(trg_mux_data),
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| 263 | .trg_flag(trg_flag));
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[27] | 264 |
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[90] | 265 | oscilloscope oscilloscope_unit (
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| 266 | .clock(sys_clock),
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| 267 | .frame(sys_frame),
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| 268 | .reset(cfg_bits[12][13]),
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| 269 | .cfg_data({cfg_bits[12][12], cfg_bits[13]}),
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| 270 | .trg_flag(trg_flag),
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| 271 | .osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
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| 272 | .ram_wren(RAM_WE),
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| 273 | .ram_addr(RAM_ADDR),
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| 274 | .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
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| 275 | .bus_ssel(bus_ssel[1]),
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| 276 | .bus_wren(bus_wren),
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| 277 | .bus_addr(bus_addr[19:0]),
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| 278 | .bus_mosi(bus_mosi),
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| 279 | .bus_miso(bus_miso[1]),
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| 280 | .bus_busy(bus_busy[1]));
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[72] | 281 |
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[90] | 282 | generate
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| 283 | for (j = 0; j < 3; j = j + 1)
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| 284 | begin : MCA_CHAIN
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[72] | 285 |
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[90] | 286 | assign int_data[j] = (cfg_bits[0][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
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| 287 |
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| 288 | uwt_bior31 #(.L(1)) uwt_1_unit (
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| 289 | .clock(sys_clock),
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| 290 | .frame(sys_frame),
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| 291 | .reset(1'b0),
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| 292 | .x({20'h00000, int_data[j]}),
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| 293 | .d(uwt_d1[j]),
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| 294 | .a(uwt_a1[j]),
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| 295 | .peak(uwt_peak1[j]),
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| 296 | .flag(uwt_flag1[j]));
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| 297 |
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| 298 | uwt_bior31 #(.L(2)) uwt_2_unit (
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| 299 | .clock(sys_clock),
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| 300 | .frame(sys_frame),
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| 301 | .reset(1'b0),
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| 302 | .x(uwt_a1[j]),
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| 303 | .d(uwt_d2[j]),
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| 304 | .a(uwt_a2[j]),
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| 305 | .peak(uwt_peak2[j]),
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| 306 | .flag(uwt_flag2[j]));
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| 307 |
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| 308 | uwt_bior31 #(.L(3)) uwt_3_unit (
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| 309 | .clock(sys_clock),
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| 310 | .frame(sys_frame),
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| 311 | .reset(1'b0),
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| 312 | .x(uwt_a2[j]),
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| 313 | .d(uwt_d3[j]),
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| 314 | .a(uwt_a3[j]),
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| 315 | .peak(uwt_peak3[j]),
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| 316 | .flag(uwt_flag3[j]));
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| 317 |
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[44] | 318 | analyser analyser_unit (
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[90] | 319 | .clock(sys_clock),
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| 320 | .frame(sys_frame),
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| 321 | .reset(cfg_bits[2+2*j][12]),
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| 322 | .cfg_data({cfg_bits[2+2*j][11:0], cfg_bits[1+2*j][12:0]}),
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| 323 | .uwt_flag(uwt_flag3[j]),
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| 324 | .uwt_data(uwt_peak3[j]),
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| 325 | .ana_good(ana_good[j]),
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| 326 | .ana_data(ana_data[j]),
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| 327 | .ana_base(ana_base[j]));
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[54] | 328 |
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[90] | 329 | histogram histogram_unit (
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| 330 | .clock(sys_clock),
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| 331 | .frame(sys_frame),
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| 332 | .reset(cfg_bits[7+j][13]),
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| 333 | .cfg_data(cfg_bits[7+j][12:0]),
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| 334 | .hst_good(ana_good[j]),
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| 335 | .hst_data(ana_data[j]),
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| 336 | .bus_ssel(bus_ssel[2+j]),
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| 337 | .bus_wren(bus_wren),
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| 338 | .bus_addr(bus_addr[12:0]),
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| 339 | .bus_mosi(bus_mosi),
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| 340 | .bus_miso(bus_miso[2+j]),
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| 341 | .bus_busy(bus_busy[2+j]));
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[84] | 342 |
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[44] | 343 | end
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| 344 | endgenerate
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[27] | 345 |
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[68] | 346 | i2c_fifo i2c_unit(
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[90] | 347 | .clock(sys_clock),
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| 348 | .reset(i2c_reset),
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[70] | 349 | /*
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| 350 | normal connection
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[68] | 351 | .i2c_sda(I2C_SDA),
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[70] | 352 | .i2c_scl(I2C_SCL),
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[68] | 353 |
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[70] | 354 | following is a cross wire connection for EPT
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| 355 | */
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| 356 | .i2c_sda(I2C_SCL),
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[90] | 357 | .i2c_scl(I2C_SDA),
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| 358 |
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| 359 | .bus_ssel(bus_ssel[5]),
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| 360 | .bus_wren(bus_wren),
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| 361 | .bus_mosi(bus_mosi),
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| 362 | .bus_busy(bus_busy[5]));
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[70] | 363 |
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[90] | 364 | generate
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| 365 | for (j = 0; j < 5; j = j + 1)
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| 366 | begin : BUS_OUTPUT
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| 367 | assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
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| 368 | end
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| 369 | endgenerate
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| 370 |
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| 371 | lpm_mux #(
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| 372 | .lpm_size(5),
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| 373 | .lpm_type("LPM_MUX"),
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| 374 | .lpm_width(16),
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| 375 | .lpm_widths(3)) bus_miso_mux_unit (
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| 376 | .sel(bus_addr[30:28]),
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| 377 | .data(int_bus_miso),
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| 378 | .result(mrg_bus_miso));
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| 379 |
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| 380 | lpm_mux #(
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| 381 | .lpm_size(6),
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| 382 | .lpm_type("LPM_MUX"),
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| 383 | .lpm_width(1),
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| 384 | .lpm_widths(3)) bus_busy_mux_unit (
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| 385 | .sel(bus_addr[30:28]),
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| 386 | .data(bus_busy),
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| 387 | .result(mrg_bus_busy));
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| 388 |
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| 389 | /*
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| 390 | lpm_or #(
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| 391 | .lpm_size(6),
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| 392 | .lpm_type("LPM_OR"),
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| 393 | .lpm_width(16)) bus_miso_or_unit (
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| 394 | .data(int_bus_miso),
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| 395 | .result(mrg_bus_miso));
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| 396 | */
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| 397 |
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| 398 | lpm_decode #(
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| 399 | .lpm_decodes(8),
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| 400 | .lpm_type("LPM_DECODE"),
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| 401 | .lpm_width(3)) lpm_decode_unit (
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| 402 | .data(bus_addr[30:28]),
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| 403 | .eq(bus_ssel),
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| 404 | .aclr(),
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| 405 | .clken(),
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| 406 | .clock(),
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| 407 | .enable());
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| 408 |
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[59] | 409 | control control_unit (
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[90] | 410 | .clock(sys_clock),
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[59] | 411 | .rx_empty(usb_rx_empty),
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| 412 | .tx_full(usb_tx_full),
|
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| 413 | .rx_data(usb_rx_data),
|
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| 414 | .rx_rdreq(usb_rx_rdreq),
|
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| 415 | .tx_wrreq(usb_tx_wrreq),
|
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| 416 | .tx_data(usb_tx_data),
|
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[90] | 417 | .bus_wren(bus_wren),
|
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| 418 | .bus_addr(bus_addr),
|
---|
| 419 | .bus_mosi(bus_mosi),
|
---|
| 420 | .bus_miso(mrg_bus_miso),
|
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| 421 | .bus_busy(mrg_bus_busy),
|
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[59] | 422 | .led(LED));
|
---|
[45] | 423 |
|
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[84] | 424 | /*
|
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| 425 | altserial_flash_loader #(
|
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| 426 | .enable_shared_access("OFF"),
|
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| 427 | .enhanced_mode(1),
|
---|
| 428 | .intended_device_family("Cyclone III")) sfl_unit (
|
---|
| 429 | .noe(1'b0),
|
---|
| 430 | .asmi_access_granted(),
|
---|
| 431 | .asmi_access_request(),
|
---|
| 432 | .data0out(),
|
---|
| 433 | .dclkin(),
|
---|
| 434 | .scein(),
|
---|
| 435 | .sdoin());
|
---|
| 436 | */
|
---|
| 437 |
|
---|
[54] | 438 | endmodule
|
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