| [27] | 1 | module Paella
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| 2 | (
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| 3 | input wire CLK_50MHz,
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| 4 | output wire LED,
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| 5 |
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| 6 | inout wire [3:0] TRG,
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| [68] | 7 | inout wire I2C_SDA,
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| [72] | 8 | inout wire I2C_SCL,
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| [68] | 9 | inout wire [4:0] CON_A,
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| [84] | 10 | input wire [15:0] CON_B,
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| [63] | 11 | input wire [12:0] CON_C,
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| [27] | 12 | input wire [1:0] CON_BCLK,
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| 13 | input wire [1:0] CON_CCLK,
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| 14 |
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| 15 | input wire ADC_DCO,
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| 16 | input wire ADC_FCO,
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| [41] | 17 | input wire [2:0] ADC_D,
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| [27] | 18 |
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| 19 | output wire USB_SLRD,
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| 20 | output wire USB_SLWR,
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| 21 | input wire USB_IFCLK,
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| 22 | input wire USB_FLAGA, // EMPTY flag for EP6
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| 23 | input wire USB_FLAGB, // FULL flag for EP8
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| 24 | input wire USB_FLAGC,
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| [30] | 25 | inout wire USB_PA0,
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| 26 | inout wire USB_PA1,
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| 27 | output wire USB_PA2,
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| 28 | inout wire USB_PA3,
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| 29 | output wire USB_PA4,
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| 30 | output wire USB_PA5,
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| 31 | output wire USB_PA6,
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| 32 | inout wire USB_PA7,
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| [27] | 33 | inout wire [7:0] USB_PB,
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| 34 |
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| 35 | output wire RAM_CLK,
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| 36 | output wire RAM_CE1,
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| 37 | output wire RAM_WE,
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| 38 | output wire [19:0] RAM_ADDR,
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| 39 | inout wire RAM_DQAP,
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| 40 | inout wire [7:0] RAM_DQA,
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| 41 | inout wire RAM_DQBP,
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| 42 | inout wire [7:0] RAM_DQB
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| 43 | );
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| 44 |
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| [72] | 45 | localparam N = 3;
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| 46 |
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| [27] | 47 | // Turn output ports off
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| [65] | 48 | /*
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| [27] | 49 | assign RAM_CLK = 1'b0;
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| 50 | assign RAM_CE1 = 1'b0;
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| 51 | assign RAM_WE = 1'b0;
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| 52 | assign RAM_ADDR = 20'h00000;
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| [65] | 53 | */
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| [84] | 54 | assign RAM_CLK = sys_clk;
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| [65] | 55 | assign RAM_CE1 = 1'b0;
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| [27] | 56 |
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| 57 | // Turn inout ports to tri-state
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| 58 | assign TRG = 4'bz;
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| [68] | 59 | assign CON_A = 5'bz;
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| [30] | 60 | assign USB_PA0 = 1'bz;
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| 61 | assign USB_PA1 = 1'bz;
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| 62 | assign USB_PA3 = 1'bz;
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| 63 | assign USB_PA7 = 1'bz;
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| [65] | 64 | // assign RAM_DQAP = 1'bz;
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| 65 | // assign RAM_DQA = 8'bz;
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| 66 | // assign RAM_DQBP = 1'bz;
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| 67 | // assign RAM_DQB = 8'bz;
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| [27] | 68 |
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| [30] | 69 | assign USB_PA2 = ~usb_rden;
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| 70 | assign USB_PA4 = usb_addr[0];
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| 71 | assign USB_PA5 = usb_addr[1];
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| 72 | assign USB_PA6 = ~usb_pktend;
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| 73 |
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| [27] | 74 | wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
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| [59] | 75 | wire usb_aclr;
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| 76 | wire usb_tx_wrreq, usb_rx_rdreq;
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| 77 | wire usb_tx_full, usb_rx_empty;
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| 78 | wire [7:0] usb_tx_data, usb_rx_data;
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| [27] | 79 | wire [1:0] usb_addr;
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| 80 |
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| 81 | assign USB_SLRD = ~usb_rdreq;
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| 82 | assign USB_SLWR = ~usb_wrreq;
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| 83 |
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| [59] | 84 | usb_fifo usb_unit
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| [27] | 85 | (
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| 86 | .usb_clk(USB_IFCLK),
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| 87 | .usb_data(USB_PB),
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| 88 | .usb_full(~USB_FLAGB),
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| 89 | .usb_empty(~USB_FLAGA),
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| 90 | .usb_wrreq(usb_wrreq),
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| 91 | .usb_rdreq(usb_rdreq),
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| 92 | .usb_rden(usb_rden),
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| 93 | .usb_pktend(usb_pktend),
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| 94 | .usb_addr(usb_addr),
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| [34] | 95 |
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| [84] | 96 | .clk(sys_clk),
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| [59] | 97 | .aclr(usb_aclr),
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| [34] | 98 |
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| [59] | 99 | .tx_full(usb_tx_full),
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| 100 | .tx_wrreq(usb_tx_wrreq),
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| 101 | .tx_data(usb_tx_data),
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| [34] | 102 |
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| [59] | 103 | .rx_empty(usb_rx_empty),
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| 104 | .rx_rdreq(usb_rx_rdreq),
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| 105 | .rx_q(usb_rx_data)
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| [27] | 106 | );
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| [84] | 107 |
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| [72] | 108 | reg bln_reset [N-1:0];
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| 109 | wire [11:0] baseline [N-1:0];
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| 110 | wire [11:0] bln_baseline [N-1:0];
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| [44] | 111 |
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| [72] | 112 | reg ana_reset [N-1:0];
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| 113 | wire ana_peak_ready [N-1:0];
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| [84] | 114 | wire ana_peak_debug [N-1:0];
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| [44] | 115 |
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| [72] | 116 | reg osc_reset [N-1:0];
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| 117 | reg [9:0] osc_addr [N-1:0];
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| 118 | wire [9:0] osc_start_addr [N-1:0];
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| 119 | wire [15:0] osc_q [N-1:0];
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| 120 | wire osc_trig [N-1:0];
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| [27] | 121 |
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| [72] | 122 | wire [3:0] osc_mux_sel [N-1:0];
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| 123 | wire [11:0] osc_mux_data [N-1:0];
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| 124 |
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| 125 | wire trg_reset [N-1:0];
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| 126 | wire [3:0] trg_mux_sel [N-1:0];
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| 127 | wire [11:0] trg_mux_data [N-1:0];
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| 128 | wire [11:0] trg_thrs [N-1:0];
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| 129 |
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| 130 | reg hst_reset [N-1:0];
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| 131 | reg [11:0] hst_addr [N-1:0];
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| 132 | wire hst_data_ready [N-1:0];
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| 133 | wire [11:0] hst_data [N-1:0];
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| 134 | wire [31:0] hst_q [N-1:0];
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| 135 |
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| 136 |
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| 137 | wire [3:0] hst_mux_sel [N-1:0];
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| 138 | wire [12:0] hst_mux_data [N-1:0];
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| 139 |
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| 140 | wire [3:0] bln_mux_sel [N-1:0];
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| 141 | wire [11:0] bln_mux_data [N-1:0];
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| 142 |
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| [59] | 143 | wire mux_reset, mux_type;
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| 144 | wire [1:0] mux_chan, mux_byte;
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| 145 | wire [15:0] mux_addr;
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| 146 |
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| [45] | 147 | reg [7:0] mux_q;
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| [59] | 148 | reg [1:0] mux_max_byte;
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| 149 | reg [15:0] mux_min_addr, mux_max_addr;
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| [44] | 150 |
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| [72] | 151 | wire [11:0] adc_data [N-1:0];
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| [41] | 152 |
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| [86] | 153 | wire data_ready;
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| [72] | 154 | wire [11:0] data [N-1:0];
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| 155 | wire [11:0] int_data [N-1:0];
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| [84] | 156 |
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| 157 | wire [11:0] cmp_data;
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| [45] | 158 |
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| [84] | 159 | wire [11:0] nowhere;
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| 160 |
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| 161 | wire sys_clk;
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| 162 |
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| [72] | 163 | wire [31:0] uwt_d1 [N-1:0];
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| 164 | wire [31:0] uwt_a1 [N-1:0];
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| 165 | wire [31:0] uwt_peak1 [N-1:0];
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| 166 | wire [31:0] uwt_d2 [N-1:0];
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| 167 | wire [31:0] uwt_a2 [N-1:0];
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| 168 | wire [31:0] uwt_peak2 [N-1:0];
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| 169 | wire [31:0] uwt_d3 [N-1:0];
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| 170 | wire [31:0] uwt_a3 [N-1:0];
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| 171 | wire [31:0] uwt_peak3 [N-1:0];
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| [63] | 172 |
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| [72] | 173 | wire [1:0] uwt_flag1 [N-1:0];
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| 174 | wire [1:0] uwt_flag2 [N-1:0];
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| 175 | wire [1:0] uwt_flag3 [N-1:0];
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| [63] | 176 |
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| [68] | 177 | /*
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| [63] | 178 | adc_para adc_para_unit (
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| 179 | .lvds_dco(ADC_DCO),
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| 180 | .lvds_fco(ADC_FCO),
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| 181 | .para_data_ready(CON_CCLK[0]),
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| 182 | .para_data(CON_C[11:0]),
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| [81] | 183 | .adc_data(adc_data[2]));
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| [68] | 184 | */
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| [59] | 185 | /*
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| [54] | 186 | wire adc_pll_clk;
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| 187 |
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| 188 | adc_pll adc_pll_unit(
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| 189 | .inclk0(ADC_FCO),
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| 190 | .c0(adc_pll_clk));
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| 191 | */
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| [48] | 192 |
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| [84] | 193 | sys_pll sys_pll_unit(
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| 194 | .inclk0(CLK_50MHz),
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| 195 | .c0(sys_clk));
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| 196 |
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| [59] | 197 | test test_unit(
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| [84] | 198 | .clk(ADC_FCO),
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| 199 | .data(adc_data[2]));
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| 200 | // .data(nowhere);
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| [48] | 201 |
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| [63] | 202 | adc_lvds #(
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| [81] | 203 | .size(3),
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| [63] | 204 | .width(12)) adc_lvds_unit (
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| [41] | 205 | .lvds_dco(ADC_DCO),
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| [54] | 206 | // .lvds_dco(adc_pll_clk),
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| [41] | 207 | .lvds_fco(ADC_FCO),
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| [81] | 208 | .lvds_d(ADC_D[2:0]),
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| [84] | 209 | // .adc_data({ adc_data[2],
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| 210 | .adc_data({ nowhere,
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| [81] | 211 | adc_data[1],
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| [72] | 212 | adc_data[0] }));
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| 213 |
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| 214 | reg [15:0] cfg_memory [31:0];
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| 215 | wire [15:0] cfg_src_data;
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| 216 | wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr;
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| 217 |
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| 218 | wire cfg_polarity [N-1:0];
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| 219 | wire [11:0] cfg_baseline [N-1:0];
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| 220 | wire [11:0] cfg_hst_threshold [N-1:0];
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| 221 | wire [11:0] cfg_trg_threshold [N-1:0];
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| 222 |
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| 223 | wire cfg_reset;
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| 224 |
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| 225 | integer j;
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| 226 |
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| [84] | 227 | always @(posedge sys_clk)
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| [72] | 228 | begin
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| 229 | if (cfg_reset)
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| 230 | begin
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| 231 | for(j = 0; j <= 31; j = j + 1)
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| 232 | begin
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| 233 | cfg_memory[j] <= 16'd0;
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| 234 | end
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| 235 | end
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| 236 | else
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| 237 | begin
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| 238 | cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data;
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| 239 | end
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| 240 | end
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| 241 |
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| [86] | 242 | adc_fifo #(.W(48)) adc_fifo_unit (
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| [84] | 243 | .adc_clk(ADC_FCO),
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| [86] | 244 | .adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}),
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| [84] | 245 | .clk(sys_clk),
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| [86] | 246 | .data_ready(data_ready),
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| 247 | .data({cmp_data, int_data[2], int_data[1], int_data[0]}));
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| [84] | 248 |
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| [44] | 249 | genvar i;
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| [72] | 250 |
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| [44] | 251 | generate
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| [72] | 252 | for (i = 0; i < N; i = i + 1)
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| [44] | 253 | begin : MCA_CHAIN
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| [72] | 254 |
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| 255 | assign cfg_polarity[i] = cfg_memory[10][4*i];
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| 256 | assign cfg_baseline[i] = cfg_memory[11+i][11:0];
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| 257 | assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0];
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| 258 | assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0];
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| 259 |
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| 260 | assign osc_mux_sel[i] = cfg_memory[20+i][3:0];
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| 261 | assign trg_mux_sel[i] = cfg_memory[20+i][7:4];
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| 262 |
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| [75] | 263 | assign hst_mux_sel[i] = cfg_memory[23+i][3:0];
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| 264 | assign bln_mux_sel[i] = cfg_memory[23+i][7:4];
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| 265 |
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| [72] | 266 | assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]);
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| 267 |
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| 268 | uwt_bior31 #(.L(1)) uwt_1_unit (
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| [84] | 269 | .clk(sys_clk),
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| [86] | 270 | .data_ready(data_ready),
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| [72] | 271 | .x({20'h00000, data[i]}),
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| 272 | .d(uwt_d1[i]),
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| 273 | .a(uwt_a1[i]),
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| 274 | .peak(uwt_peak1[i]),
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| 275 | .flag(uwt_flag1[i]));
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| 276 |
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| 277 | uwt_bior31 #(.L(2)) uwt_2_unit (
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| [84] | 278 | .clk(sys_clk),
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| [86] | 279 | .data_ready(data_ready),
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| [72] | 280 | .x(uwt_a1[i]),
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| 281 | .d(uwt_d2[i]),
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| 282 | .a(uwt_a2[i]),
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| 283 | .peak(uwt_peak2[i]),
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| 284 | .flag(uwt_flag2[i]));
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| 285 |
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| 286 | uwt_bior31 #(.L(3)) uwt_3_unit (
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| [84] | 287 | .clk(sys_clk),
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| [86] | 288 | .data_ready(data_ready),
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| [72] | 289 | .x(uwt_a2[i]),
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| 290 | .d(uwt_d3[i]),
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| 291 | .a(uwt_a3[i]),
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| 292 | .peak(uwt_peak3[i]),
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| 293 | .flag(uwt_flag3[i]));
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| 294 |
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| 295 | lpm_mux #(
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| [84] | 296 | .lpm_size(7),
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| [72] | 297 | .lpm_type("LPM_MUX"),
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| 298 | .lpm_width(12),
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| [75] | 299 | .lpm_widths(3)) osc_mux_unit (
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| 300 | .sel(osc_mux_sel[i][2:0]),
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| [84] | 301 | .data({ {ana_peak_debug[i], 11'd0},
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| 302 | hst_data[i],
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| 303 | // uwt_d3[i][11:0],
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| 304 | bln_baseline[i],
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| [75] | 305 | uwt_a3[i][20:9],
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| [72] | 306 | uwt_a2[i][17:6],
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| 307 | uwt_a1[i][14:3],
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| 308 | data[i] }),
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| 309 | .result(osc_mux_data[i]));
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| 310 |
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| 311 | lpm_mux #(
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| [84] | 312 | .lpm_size(7),
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| [72] | 313 | .lpm_type("LPM_MUX"),
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| 314 | .lpm_width(12),
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| [75] | 315 | .lpm_widths(3)) trg_mux_unit (
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| 316 | .sel(trg_mux_sel[i][2:0]),
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| [84] | 317 | .data({ {ana_peak_ready[i], 11'd0},
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| 318 | hst_data[i],
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| 319 | // uwt_d3[i][11:0],
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| 320 | bln_baseline[i],
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| [75] | 321 | uwt_a3[i][20:9],
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| [72] | 322 | uwt_a2[i][17:6],
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| 323 | uwt_a1[i][14:3],
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| 324 | data[i] }),
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| 325 | .result(trg_mux_data[i]));
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| 326 |
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| 327 | lpm_mux #(
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| 328 | .lpm_size(2),
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| 329 | .lpm_type("LPM_MUX"),
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| 330 | .lpm_width(13),
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| 331 | .lpm_widths(1)) hst_mux_unit (
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| 332 | .sel(hst_mux_sel[i][0]),
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| [80] | 333 | .data({ {uwt_peak3[i][11:0], ana_peak_ready[i]},
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| [86] | 334 | {data[i], data_ready} }),
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| [72] | 335 | .result(hst_mux_data[i]));
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| [27] | 336 |
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| [72] | 337 | lpm_mux #(
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| 338 | .lpm_size(2),
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| 339 | .lpm_type("LPM_MUX"),
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| 340 | .lpm_width(12),
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| 341 | .lpm_widths(1)) bln_mux_unit (
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| 342 | .sel(bln_mux_sel[i][0]),
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| 343 | .data({bln_baseline[i], cfg_baseline[i]}),
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| 344 | .result(bln_mux_data[i]));
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| 345 |
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| 346 | baseline baseline_unit (
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| [84] | 347 | .clk(sys_clk),
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| [72] | 348 | .reset(bln_reset[i]),
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| [86] | 349 | .data_ready(data_ready),
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| [72] | 350 | .uwt_flag(uwt_flag3[i]),
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| 351 | .uwt_data(uwt_peak3[i]),
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| 352 | .baseline(bln_baseline[i]));
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| 353 |
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| [44] | 354 | analyser analyser_unit (
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| [84] | 355 | .clk(sys_clk),
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| [44] | 356 | .reset(ana_reset[i]),
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| [86] | 357 | .data_ready(data_ready),
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| [72] | 358 | .uwt_flag(uwt_flag3[i]),
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| [84] | 359 | .peak_ready(ana_peak_ready[i]),
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| 360 | .peak_debug(ana_peak_debug[i]));
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| [54] | 361 |
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| [84] | 362 | suppression suppression_unit (
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| 363 | .clk(sys_clk),
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| 364 | .data(hst_mux_data[i][12:1]),
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| 365 | .baseline(bln_mux_data[i]),
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| 366 | .result(hst_data[i]));
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| 367 |
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| [72] | 368 | assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]);
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| 369 |
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| 370 | histogram #(.W(32)) histogram_unit (
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| [84] | 371 | .clk(sys_clk),
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| [44] | 372 | .reset(hst_reset[i]),
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| [72] | 373 | .data_ready(hst_data_ready[i]),
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| 374 | .data(hst_data[i]),
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| [44] | 375 | .address(hst_addr[i]),
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| 376 | .q(hst_q[i]));
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| [72] | 377 |
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| 378 | trigger trigger_unit (
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| [84] | 379 | .clk(sys_clk),
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| [72] | 380 | .reset(trg_reset[i]),
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| [86] | 381 | .data_ready(data_ready),
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| [72] | 382 | .data(trg_mux_data[i]),
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| 383 | .threshold(cfg_trg_threshold[i]),
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| 384 | .trigger(osc_trig[i]));
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| 385 |
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| 386 |
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| [44] | 387 | oscilloscope oscilloscope_unit (
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| [84] | 388 | .clk(sys_clk),
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| [44] | 389 | .reset(osc_reset[i]),
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| [86] | 390 | .data_ready(data_ready),
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| [72] | 391 | .data(osc_mux_data[i]),
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| 392 | .trigger(osc_trig[i]),
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| [44] | 393 | .address(osc_addr[i]),
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| 394 | .start_address(osc_start_addr[i]),
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| 395 | .q(osc_q[i]));
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| 396 | end
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| 397 | endgenerate
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| [27] | 398 |
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| [44] | 399 | always @*
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| [27] | 400 | begin
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| [72] | 401 | for (j = 0; j < N; j = j + 1)
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| [46] | 402 | begin
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| 403 | osc_reset[j] = 1'b0;
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| 404 | osc_addr[j] = 10'b0;
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| 405 | hst_reset[j] = 1'b0;
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| 406 | hst_addr[j] = 12'b0;
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| 407 | end
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| 408 |
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| [72] | 409 | case(mux_type)
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| 410 | 1'b0:
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| [27] | 411 | begin
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| [45] | 412 | osc_reset[mux_chan] = mux_reset;
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| 413 | osc_addr[mux_chan] = mux_addr[9:0];
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| 414 | mux_max_byte = 2'd1;
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| 415 | mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
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| [59] | 416 | mux_max_addr = 16'd1023;
|
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| [27] | 417 | end
|
|---|
| [45] | 418 |
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| [72] | 419 | 1'b1:
|
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| [27] | 420 | begin
|
|---|
| [45] | 421 | hst_reset[mux_chan] = mux_reset;
|
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| 422 | hst_addr[mux_chan] = mux_addr[11:0];
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| [70] | 423 | mux_max_byte = 2'd3;
|
|---|
| [45] | 424 | mux_min_addr = 16'd0;
|
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| [70] | 425 | mux_max_addr = 16'd4095;
|
|---|
| [27] | 426 | end
|
|---|
| 427 | endcase
|
|---|
| 428 | end
|
|---|
| [45] | 429 |
|
|---|
| 430 | always @*
|
|---|
| 431 | begin
|
|---|
| [59] | 432 | case ({mux_type, mux_byte})
|
|---|
| 433 | 3'b000: mux_q = osc_q[mux_chan][7:0];
|
|---|
| 434 | 3'b001: mux_q = osc_q[mux_chan][15:8];
|
|---|
| [35] | 435 |
|
|---|
| [59] | 436 | 3'b100: mux_q = hst_q[mux_chan][7:0];
|
|---|
| 437 | 3'b101: mux_q = hst_q[mux_chan][15:8];
|
|---|
| 438 | 3'b110: mux_q = hst_q[mux_chan][23:16];
|
|---|
| [68] | 439 | 3'b111: mux_q = hst_q[mux_chan][31:24];
|
|---|
| [45] | 440 |
|
|---|
| 441 | default: mux_q = 8'd0;
|
|---|
| 442 | endcase
|
|---|
| 443 | end
|
|---|
| [68] | 444 |
|
|---|
| 445 | wire i2c_aclr;
|
|---|
| 446 | wire i2c_wrreq;
|
|---|
| 447 | wire i2c_full;
|
|---|
| 448 | wire [15:0] i2c_data;
|
|---|
| 449 |
|
|---|
| 450 | i2c_fifo i2c_unit(
|
|---|
| [84] | 451 | .clk(sys_clk),
|
|---|
| [68] | 452 | .aclr(i2c_aclr),
|
|---|
| 453 | .wrreq(i2c_wrreq),
|
|---|
| 454 | .data(i2c_data),
|
|---|
| 455 | .full(i2c_full),
|
|---|
| [70] | 456 | /*
|
|---|
| 457 | normal connection
|
|---|
| [68] | 458 | .i2c_sda(I2C_SDA),
|
|---|
| [70] | 459 | .i2c_scl(I2C_SCL),
|
|---|
| [68] | 460 |
|
|---|
| [70] | 461 | following is a cross wire connection for EPT
|
|---|
| 462 | */
|
|---|
| 463 | .i2c_sda(I2C_SCL),
|
|---|
| 464 | .i2c_scl(I2C_SDA));
|
|---|
| 465 |
|
|---|
| [59] | 466 | control control_unit (
|
|---|
| [84] | 467 | .clk(sys_clk),
|
|---|
| [72] | 468 | .cfg_reset(cfg_reset),
|
|---|
| 469 | .cfg_src_data(cfg_memory[cfg_src_addr[4:0]]),
|
|---|
| 470 | .cfg_src_addr(cfg_src_addr),
|
|---|
| 471 | .cfg_dst_data(cfg_dst_data),
|
|---|
| 472 | .cfg_dst_addr(cfg_dst_addr),
|
|---|
| [59] | 473 | .rx_empty(usb_rx_empty),
|
|---|
| 474 | .tx_full(usb_tx_full),
|
|---|
| 475 | .rx_data(usb_rx_data),
|
|---|
| 476 | .mux_max_byte(mux_max_byte),
|
|---|
| 477 | .mux_min_addr(mux_min_addr),
|
|---|
| 478 | .mux_max_addr(mux_max_addr),
|
|---|
| 479 | .mux_q(mux_q),
|
|---|
| 480 | .mux_reset(mux_reset),
|
|---|
| 481 | .mux_type(mux_type),
|
|---|
| 482 | .mux_chan(mux_chan),
|
|---|
| 483 | .mux_byte(mux_byte),
|
|---|
| 484 | .mux_addr(mux_addr),
|
|---|
| 485 | .rx_rdreq(usb_rx_rdreq),
|
|---|
| 486 | .tx_wrreq(usb_tx_wrreq),
|
|---|
| 487 | .tx_data(usb_tx_data),
|
|---|
| [65] | 488 | .ram_we(RAM_WE),
|
|---|
| 489 | .ram_addr(RAM_ADDR),
|
|---|
| 490 | .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
|
|---|
| [86] | 491 | .ept_data_ready(data_ready),
|
|---|
| 492 | .ept_data({cmp_data, data[2], data[1], data[0]}),
|
|---|
| [68] | 493 | .i2c_wrreq(i2c_wrreq),
|
|---|
| 494 | .i2c_data(i2c_data),
|
|---|
| 495 | .i2c_full(i2c_full),
|
|---|
| [59] | 496 | .led(LED));
|
|---|
| [45] | 497 |
|
|---|
| [84] | 498 | /*
|
|---|
| 499 | altserial_flash_loader #(
|
|---|
| 500 | .enable_shared_access("OFF"),
|
|---|
| 501 | .enhanced_mode(1),
|
|---|
| 502 | .intended_device_family("Cyclone III")) sfl_unit (
|
|---|
| 503 | .noe(1'b0),
|
|---|
| 504 | .asmi_access_granted(),
|
|---|
| 505 | .asmi_access_request(),
|
|---|
| 506 | .data0out(),
|
|---|
| 507 | .dclkin(),
|
|---|
| 508 | .scein(),
|
|---|
| 509 | .sdoin());
|
|---|
| 510 | */
|
|---|
| 511 |
|
|---|
| [54] | 512 | endmodule
|
|---|
