source: trunk/MultiChannelUSB/Paella.v@ 84

Last change on this file since 84 was 84, checked in by demin, 15 years ago

improve timings in all components
File size: 12.4 KB
RevLine 
[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
[68]7 inout wire I2C_SDA,
[72]8 inout wire I2C_SCL,
[68]9 inout wire [4:0] CON_A,
[84]10 input wire [15:0] CON_B,
[63]11 input wire [12:0] CON_C,
[27]12 input wire [1:0] CON_BCLK,
13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
[41]17 input wire [2:0] ADC_D,
[27]18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
[30]25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
[27]33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
[72]45 localparam N = 3;
46
[27]47 // Turn output ports off
[65]48/*
[27]49 assign RAM_CLK = 1'b0;
50 assign RAM_CE1 = 1'b0;
51 assign RAM_WE = 1'b0;
52 assign RAM_ADDR = 20'h00000;
[65]53*/
[84]54 assign RAM_CLK = sys_clk;
[65]55 assign RAM_CE1 = 1'b0;
[27]56
57 // Turn inout ports to tri-state
58 assign TRG = 4'bz;
[68]59 assign CON_A = 5'bz;
[30]60 assign USB_PA0 = 1'bz;
61 assign USB_PA1 = 1'bz;
62 assign USB_PA3 = 1'bz;
63 assign USB_PA7 = 1'bz;
[65]64// assign RAM_DQAP = 1'bz;
65// assign RAM_DQA = 8'bz;
66// assign RAM_DQBP = 1'bz;
67// assign RAM_DQB = 8'bz;
[27]68
[30]69 assign USB_PA2 = ~usb_rden;
70 assign USB_PA4 = usb_addr[0];
71 assign USB_PA5 = usb_addr[1];
72 assign USB_PA6 = ~usb_pktend;
73
[27]74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[59]75 wire usb_aclr;
76 wire usb_tx_wrreq, usb_rx_rdreq;
77 wire usb_tx_full, usb_rx_empty;
78 wire [7:0] usb_tx_data, usb_rx_data;
[27]79 wire [1:0] usb_addr;
80
81 assign USB_SLRD = ~usb_rdreq;
82 assign USB_SLWR = ~usb_wrreq;
83
[59]84 usb_fifo usb_unit
[27]85 (
86 .usb_clk(USB_IFCLK),
87 .usb_data(USB_PB),
88 .usb_full(~USB_FLAGB),
89 .usb_empty(~USB_FLAGA),
90 .usb_wrreq(usb_wrreq),
91 .usb_rdreq(usb_rdreq),
92 .usb_rden(usb_rden),
93 .usb_pktend(usb_pktend),
94 .usb_addr(usb_addr),
[34]95
[84]96 .clk(sys_clk),
[59]97 .aclr(usb_aclr),
[34]98
[59]99 .tx_full(usb_tx_full),
100 .tx_wrreq(usb_tx_wrreq),
101 .tx_data(usb_tx_data),
[34]102
[59]103 .rx_empty(usb_rx_empty),
104 .rx_rdreq(usb_rx_rdreq),
105 .rx_q(usb_rx_data)
[27]106 );
[84]107
[72]108 reg bln_reset [N-1:0];
109 wire [11:0] baseline [N-1:0];
110 wire [11:0] bln_baseline [N-1:0];
[44]111
[72]112 reg ana_reset [N-1:0];
113 wire ana_peak_ready [N-1:0];
[84]114 wire ana_peak_debug [N-1:0];
[44]115
[72]116 reg osc_reset [N-1:0];
117 reg [9:0] osc_addr [N-1:0];
118 wire [9:0] osc_start_addr [N-1:0];
119 wire [15:0] osc_q [N-1:0];
120 wire osc_trig [N-1:0];
[27]121
[72]122 wire [3:0] osc_mux_sel [N-1:0];
123 wire [11:0] osc_mux_data [N-1:0];
124
125 wire trg_reset [N-1:0];
126 wire [3:0] trg_mux_sel [N-1:0];
127 wire [11:0] trg_mux_data [N-1:0];
128 wire [11:0] trg_thrs [N-1:0];
129
130 reg hst_reset [N-1:0];
131 reg [11:0] hst_addr [N-1:0];
132 wire hst_data_ready [N-1:0];
133 wire [11:0] hst_data [N-1:0];
134 wire [31:0] hst_q [N-1:0];
135
136
137 wire [3:0] hst_mux_sel [N-1:0];
138 wire [12:0] hst_mux_data [N-1:0];
139
140 wire [3:0] bln_mux_sel [N-1:0];
141 wire [11:0] bln_mux_data [N-1:0];
142
[59]143 wire mux_reset, mux_type;
144 wire [1:0] mux_chan, mux_byte;
145 wire [15:0] mux_addr;
146
[45]147 reg [7:0] mux_q;
[59]148 reg [1:0] mux_max_byte;
149 reg [15:0] mux_min_addr, mux_max_addr;
[44]150
[72]151 wire adc_clk [N-1:0];
152 wire [11:0] adc_data [N-1:0];
[41]153
[72]154 wire data_ready [N-1:0];
155 wire [11:0] data [N-1:0];
156 wire [11:0] int_data [N-1:0];
[84]157
158 wire cmp_data_ready;
159 wire [11:0] cmp_data;
160
161 wire ept_data_ready;
162 wire [47:0] ept_data;
[45]163
[84]164 wire [11:0] nowhere;
165
166 wire sys_clk;
167
168
[72]169/*
[63]170 assign osc_thrs[0] = 16'd40;
[68]171 assign osc_thrs[1] = 16'd60;
[63]172 assign osc_thrs[2] = 16'd40;
173 assign osc_thrs[3] = 16'd1650;
[72]174*/
175 wire [31:0] uwt_d1 [N-1:0];
176 wire [31:0] uwt_a1 [N-1:0];
177 wire [31:0] uwt_peak1 [N-1:0];
178 wire [31:0] uwt_d2 [N-1:0];
179 wire [31:0] uwt_a2 [N-1:0];
180 wire [31:0] uwt_peak2 [N-1:0];
181 wire [31:0] uwt_d3 [N-1:0];
182 wire [31:0] uwt_a3 [N-1:0];
183 wire [31:0] uwt_peak3 [N-1:0];
[63]184
[72]185 wire [1:0] uwt_flag1 [N-1:0];
186 wire [1:0] uwt_flag2 [N-1:0];
187 wire [1:0] uwt_flag3 [N-1:0];
[63]188
[84]189 assign adc_clk[0] = ADC_FCO;
190 assign adc_clk[1] = ADC_FCO;
191 assign adc_clk[2] = ADC_FCO;
[81]192
[63]193/*
[81]194 assign adc_clk[2] = CON_CCLK[0];
195 assign adc_data[2] = CON_C[11:0];
[63]196*/
[68]197/*
[63]198 adc_para adc_para_unit (
199 .lvds_dco(ADC_DCO),
200 .lvds_fco(ADC_FCO),
201 .para_data_ready(CON_CCLK[0]),
202 .para_data(CON_C[11:0]),
[81]203 .adc_data(adc_data[2]));
[68]204*/
[59]205/*
[54]206 wire adc_pll_clk;
207
208 adc_pll adc_pll_unit(
209 .inclk0(ADC_FCO),
210 .c0(adc_pll_clk));
211*/
[48]212
[84]213 sys_pll sys_pll_unit(
214 .inclk0(CLK_50MHz),
215 .c0(sys_clk));
216
[59]217 test test_unit(
[84]218 .clk(ADC_FCO),
219 .data(adc_data[2]));
220// .data(nowhere);
[48]221
[72]222
[63]223 adc_lvds #(
[81]224 .size(3),
[63]225 .width(12)) adc_lvds_unit (
[41]226 .lvds_dco(ADC_DCO),
[54]227// .lvds_dco(adc_pll_clk),
[41]228 .lvds_fco(ADC_FCO),
[81]229 .lvds_d(ADC_D[2:0]),
[84]230// .adc_data({ adc_data[2],
231 .adc_data({ nowhere,
[81]232 adc_data[1],
[72]233 adc_data[0] }));
234
235
236 reg [15:0] cfg_memory [31:0];
237 wire [15:0] cfg_src_data;
238 wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr;
239
240 wire cfg_polarity [N-1:0];
241 wire [11:0] cfg_baseline [N-1:0];
242 wire [11:0] cfg_hst_threshold [N-1:0];
243 wire [11:0] cfg_trg_threshold [N-1:0];
244
245 wire cfg_reset;
246
247 integer j;
248
[84]249 always @(posedge sys_clk)
[72]250 begin
251 if (cfg_reset)
252 begin
253 for(j = 0; j <= 31; j = j + 1)
254 begin
255 cfg_memory[j] <= 16'd0;
256 end
257 end
258 else
259 begin
260 cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data;
261 end
262 end
263
[84]264 assign ept_data_ready = cmp_data_ready & data_ready[2] & data_ready[1] & data_ready[0];
265 assign ept_data = {cmp_data, int_data[2], int_data[1], int_data[0]};
266
267 adc_fifo cmp_fifo_unit (
268 .adc_clk(ADC_FCO),
269 .adc_data(CON_B[11:0]),
270 .clk(sys_clk),
271 .data_ready(cmp_data_ready),
272 .data(cmp_data));
273
[44]274 genvar i;
[72]275
[44]276 generate
[72]277 for (i = 0; i < N; i = i + 1)
[44]278 begin : MCA_CHAIN
[72]279
280 assign cfg_polarity[i] = cfg_memory[10][4*i];
281 assign cfg_baseline[i] = cfg_memory[11+i][11:0];
282 assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0];
283 assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0];
284
285 assign osc_mux_sel[i] = cfg_memory[20+i][3:0];
286 assign trg_mux_sel[i] = cfg_memory[20+i][7:4];
287
[75]288 assign hst_mux_sel[i] = cfg_memory[23+i][3:0];
289 assign bln_mux_sel[i] = cfg_memory[23+i][7:4];
290
[44]291 adc_fifo adc_fifo_unit (
[45]292 .adc_clk(adc_clk[i]),
293 .adc_data(adc_data[i]),
[84]294 .clk(sys_clk),
[72]295 .data_ready(data_ready[i]),
296 .data(int_data[i]));
297
298 assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]);
299
300 uwt_bior31 #(.L(1)) uwt_1_unit (
[84]301 .clk(sys_clk),
[72]302 .data_ready(data_ready[i]),
303 .x({20'h00000, data[i]}),
304 .d(uwt_d1[i]),
305 .a(uwt_a1[i]),
306 .peak(uwt_peak1[i]),
307 .flag(uwt_flag1[i]));
308
309 uwt_bior31 #(.L(2)) uwt_2_unit (
[84]310 .clk(sys_clk),
[72]311 .data_ready(data_ready[i]),
312 .x(uwt_a1[i]),
313 .d(uwt_d2[i]),
314 .a(uwt_a2[i]),
315 .peak(uwt_peak2[i]),
316 .flag(uwt_flag2[i]));
317
318 uwt_bior31 #(.L(3)) uwt_3_unit (
[84]319 .clk(sys_clk),
[72]320 .data_ready(data_ready[i]),
321 .x(uwt_a2[i]),
322 .d(uwt_d3[i]),
323 .a(uwt_a3[i]),
324 .peak(uwt_peak3[i]),
325 .flag(uwt_flag3[i]));
326
327 lpm_mux #(
[84]328 .lpm_size(7),
[72]329 .lpm_type("LPM_MUX"),
330 .lpm_width(12),
[75]331 .lpm_widths(3)) osc_mux_unit (
332 .sel(osc_mux_sel[i][2:0]),
[84]333 .data({ {ana_peak_debug[i], 11'd0},
334 hst_data[i],
335// uwt_d3[i][11:0],
336 bln_baseline[i],
[75]337 uwt_a3[i][20:9],
[72]338 uwt_a2[i][17:6],
339 uwt_a1[i][14:3],
340 data[i] }),
341 .result(osc_mux_data[i]));
342
343 lpm_mux #(
[84]344 .lpm_size(7),
[72]345 .lpm_type("LPM_MUX"),
346 .lpm_width(12),
[75]347 .lpm_widths(3)) trg_mux_unit (
348 .sel(trg_mux_sel[i][2:0]),
[84]349 .data({ {ana_peak_ready[i], 11'd0},
350 hst_data[i],
351// uwt_d3[i][11:0],
352 bln_baseline[i],
[75]353 uwt_a3[i][20:9],
[72]354 uwt_a2[i][17:6],
355 uwt_a1[i][14:3],
356 data[i] }),
357 .result(trg_mux_data[i]));
358
359 lpm_mux #(
360 .lpm_size(2),
361 .lpm_type("LPM_MUX"),
362 .lpm_width(13),
363 .lpm_widths(1)) hst_mux_unit (
364 .sel(hst_mux_sel[i][0]),
[80]365 .data({ {uwt_peak3[i][11:0], ana_peak_ready[i]},
[72]366 {data[i], data_ready[i]} }),
367 .result(hst_mux_data[i]));
[27]368
[72]369 lpm_mux #(
370 .lpm_size(2),
371 .lpm_type("LPM_MUX"),
372 .lpm_width(12),
373 .lpm_widths(1)) bln_mux_unit (
374 .sel(bln_mux_sel[i][0]),
375 .data({bln_baseline[i], cfg_baseline[i]}),
376 .result(bln_mux_data[i]));
377
378 baseline baseline_unit (
[84]379 .clk(sys_clk),
[72]380 .reset(bln_reset[i]),
381 .data_ready(data_ready[i]),
382 .uwt_flag(uwt_flag3[i]),
383 .uwt_data(uwt_peak3[i]),
384 .baseline(bln_baseline[i]));
385
[44]386 analyser analyser_unit (
[84]387 .clk(sys_clk),
[44]388 .reset(ana_reset[i]),
[72]389 .data_ready(data_ready[i]),
390 .uwt_flag(uwt_flag3[i]),
[84]391 .peak_ready(ana_peak_ready[i]),
392 .peak_debug(ana_peak_debug[i]));
[54]393
[84]394 suppression suppression_unit (
395 .clk(sys_clk),
396 .data(hst_mux_data[i][12:1]),
397 .baseline(bln_mux_data[i]),
398 .result(hst_data[i]));
399
[72]400 assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]);
401
402 histogram #(.W(32)) histogram_unit (
[84]403 .clk(sys_clk),
[44]404 .reset(hst_reset[i]),
[72]405 .data_ready(hst_data_ready[i]),
406 .data(hst_data[i]),
[44]407 .address(hst_addr[i]),
408 .q(hst_q[i]));
[72]409
410 trigger trigger_unit (
[84]411 .clk(sys_clk),
[72]412 .reset(trg_reset[i]),
413 .data_ready(data_ready[i]),
414 .data(trg_mux_data[i]),
415 .threshold(cfg_trg_threshold[i]),
416 .trigger(osc_trig[i]));
417
418
[44]419 oscilloscope oscilloscope_unit (
[84]420 .clk(sys_clk),
[44]421 .reset(osc_reset[i]),
[72]422 .data_ready(data_ready[i]),
423 .data(osc_mux_data[i]),
424 .trigger(osc_trig[i]),
[44]425 .address(osc_addr[i]),
426 .start_address(osc_start_addr[i]),
427 .q(osc_q[i]));
428 end
429 endgenerate
[27]430
[44]431 always @*
[27]432 begin
[72]433 for (j = 0; j < N; j = j + 1)
[46]434 begin
435 osc_reset[j] = 1'b0;
436 osc_addr[j] = 10'b0;
437 hst_reset[j] = 1'b0;
438 hst_addr[j] = 12'b0;
439 end
440
[72]441 case(mux_type)
442// case({mux_type, mux_chan})
443 1'b0:
444// 3'b000, 3'b001, 3'b010, 3'b011:
[27]445 begin
[45]446 osc_reset[mux_chan] = mux_reset;
447 osc_addr[mux_chan] = mux_addr[9:0];
448 mux_max_byte = 2'd1;
449 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
[59]450 mux_max_addr = 16'd1023;
[27]451 end
[45]452
[72]453 1'b1:
454// 3'b100, 3'b101, 3'b110, 3'b011:
[27]455 begin
[45]456 hst_reset[mux_chan] = mux_reset;
457 hst_addr[mux_chan] = mux_addr[11:0];
[70]458 mux_max_byte = 2'd3;
[45]459 mux_min_addr = 16'd0;
[70]460 mux_max_addr = 16'd4095;
[27]461 end
462 endcase
463 end
[45]464
465 always @*
466 begin
[59]467 case ({mux_type, mux_byte})
468 3'b000: mux_q = osc_q[mux_chan][7:0];
469 3'b001: mux_q = osc_q[mux_chan][15:8];
[35]470
[59]471 3'b100: mux_q = hst_q[mux_chan][7:0];
472 3'b101: mux_q = hst_q[mux_chan][15:8];
473 3'b110: mux_q = hst_q[mux_chan][23:16];
[68]474 3'b111: mux_q = hst_q[mux_chan][31:24];
[45]475
476 default: mux_q = 8'd0;
477 endcase
478 end
[68]479
480 wire i2c_aclr;
481 wire i2c_wrreq;
482 wire i2c_full;
483 wire [15:0] i2c_data;
484
485 i2c_fifo i2c_unit(
[84]486 .clk(sys_clk),
[68]487 .aclr(i2c_aclr),
488 .wrreq(i2c_wrreq),
489 .data(i2c_data),
490 .full(i2c_full),
[70]491/*
492 normal connection
[68]493 .i2c_sda(I2C_SDA),
[70]494 .i2c_scl(I2C_SCL),
[68]495
[70]496 following is a cross wire connection for EPT
497*/
498 .i2c_sda(I2C_SCL),
499 .i2c_scl(I2C_SDA));
500
[59]501 control control_unit (
[84]502 .clk(sys_clk),
[72]503 .cfg_reset(cfg_reset),
504 .cfg_src_data(cfg_memory[cfg_src_addr[4:0]]),
505 .cfg_src_addr(cfg_src_addr),
506 .cfg_dst_data(cfg_dst_data),
507 .cfg_dst_addr(cfg_dst_addr),
[59]508 .rx_empty(usb_rx_empty),
509 .tx_full(usb_tx_full),
510 .rx_data(usb_rx_data),
511 .mux_max_byte(mux_max_byte),
512 .mux_min_addr(mux_min_addr),
513 .mux_max_addr(mux_max_addr),
514 .mux_q(mux_q),
515 .mux_reset(mux_reset),
516 .mux_type(mux_type),
517 .mux_chan(mux_chan),
518 .mux_byte(mux_byte),
519 .mux_addr(mux_addr),
520 .rx_rdreq(usb_rx_rdreq),
521 .tx_wrreq(usb_tx_wrreq),
522 .tx_data(usb_tx_data),
[65]523 .ram_we(RAM_WE),
524 .ram_addr(RAM_ADDR),
525 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
[84]526 .ept_data_ready(ept_data_ready),
527 .ept_data(ept_data),
[68]528 .i2c_wrreq(i2c_wrreq),
529 .i2c_data(i2c_data),
530 .i2c_full(i2c_full),
[59]531 .led(LED));
[45]532
[84]533/*
534 altserial_flash_loader #(
535 .enable_shared_access("OFF"),
536 .enhanced_mode(1),
537 .intended_device_family("Cyclone III")) sfl_unit (
538 .noe(1'b0),
539 .asmi_access_granted(),
540 .asmi_access_request(),
541 .data0out(),
542 .dclkin(),
543 .scein(),
544 .sdoin());
545*/
546
[54]547endmodule
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