source: trunk/MultiChannelUSB/Paella.v@ 81

Last change on this file since 81 was 81, checked in by demin, 15 years ago

activate all 3 ADC channels
File size: 11.7 KB
RevLine 
[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
[68]7 inout wire I2C_SDA,
[72]8 inout wire I2C_SCL,
[68]9 inout wire [4:0] CON_A,
[27]10 inout wire [15:0] CON_B,
[63]11 input wire [12:0] CON_C,
[27]12 input wire [1:0] CON_BCLK,
13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
[41]17 input wire [2:0] ADC_D,
[27]18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
[30]25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
[27]33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
[72]45 localparam N = 3;
46
[27]47 // Turn output ports off
[65]48/*
[27]49 assign RAM_CLK = 1'b0;
50 assign RAM_CE1 = 1'b0;
51 assign RAM_WE = 1'b0;
52 assign RAM_ADDR = 20'h00000;
[65]53*/
54 assign RAM_CLK = CLK_50MHz;
55 assign RAM_CE1 = 1'b0;
[27]56
57 // Turn inout ports to tri-state
58 assign TRG = 4'bz;
[68]59 assign CON_A = 5'bz;
[27]60 assign CON_B = 16'bz;
[30]61 assign USB_PA0 = 1'bz;
62 assign USB_PA1 = 1'bz;
63 assign USB_PA3 = 1'bz;
64 assign USB_PA7 = 1'bz;
[65]65// assign RAM_DQAP = 1'bz;
66// assign RAM_DQA = 8'bz;
67// assign RAM_DQBP = 1'bz;
68// assign RAM_DQB = 8'bz;
[27]69
[30]70 assign USB_PA2 = ~usb_rden;
71 assign USB_PA4 = usb_addr[0];
72 assign USB_PA5 = usb_addr[1];
73 assign USB_PA6 = ~usb_pktend;
74
[27]75 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[59]76 wire usb_aclr;
77 wire usb_tx_wrreq, usb_rx_rdreq;
78 wire usb_tx_full, usb_rx_empty;
79 wire [7:0] usb_tx_data, usb_rx_data;
[27]80 wire [1:0] usb_addr;
81
82 assign USB_SLRD = ~usb_rdreq;
83 assign USB_SLWR = ~usb_wrreq;
84
[59]85 usb_fifo usb_unit
[27]86 (
87 .usb_clk(USB_IFCLK),
88 .usb_data(USB_PB),
89 .usb_full(~USB_FLAGB),
90 .usb_empty(~USB_FLAGA),
91 .usb_wrreq(usb_wrreq),
92 .usb_rdreq(usb_rdreq),
93 .usb_rden(usb_rden),
94 .usb_pktend(usb_pktend),
95 .usb_addr(usb_addr),
[34]96
[27]97 .clk(CLK_50MHz),
[59]98 .aclr(usb_aclr),
[34]99
[59]100 .tx_full(usb_tx_full),
101 .tx_wrreq(usb_tx_wrreq),
102 .tx_data(usb_tx_data),
[34]103
[59]104 .rx_empty(usb_rx_empty),
105 .rx_rdreq(usb_rx_rdreq),
106 .rx_q(usb_rx_data)
[27]107 );
108
[72]109 reg bln_reset [N-1:0];
110 wire [11:0] baseline [N-1:0];
111 wire [11:0] bln_baseline [N-1:0];
[44]112
[72]113 reg ana_reset [N-1:0];
114 wire ana_peak_ready [N-1:0];
[44]115
[72]116 reg osc_reset [N-1:0];
117 reg [9:0] osc_addr [N-1:0];
118 wire [9:0] osc_start_addr [N-1:0];
119 wire [15:0] osc_q [N-1:0];
120 wire osc_trig [N-1:0];
[27]121
[72]122 wire [3:0] osc_mux_sel [N-1:0];
123 wire [11:0] osc_mux_data [N-1:0];
124
125 wire trg_reset [N-1:0];
126 wire [3:0] trg_mux_sel [N-1:0];
127 wire [11:0] trg_mux_data [N-1:0];
128 wire [11:0] trg_thrs [N-1:0];
129
130 reg hst_reset [N-1:0];
131 reg [11:0] hst_addr [N-1:0];
132 wire hst_data_ready [N-1:0];
133 wire [11:0] hst_data [N-1:0];
134 wire [31:0] hst_q [N-1:0];
135
136
137 wire [3:0] hst_mux_sel [N-1:0];
138 wire [12:0] hst_mux_data [N-1:0];
139
140 wire [3:0] bln_mux_sel [N-1:0];
141 wire [11:0] bln_mux_data [N-1:0];
142
[59]143 wire mux_reset, mux_type;
144 wire [1:0] mux_chan, mux_byte;
145 wire [15:0] mux_addr;
146
[45]147 reg [7:0] mux_q;
[59]148 reg [1:0] mux_max_byte;
149 reg [15:0] mux_min_addr, mux_max_addr;
[44]150
[72]151 wire adc_clk [N-1:0];
152 wire [11:0] adc_data [N-1:0];
[41]153
[72]154 wire data_ready [N-1:0];
155 wire [11:0] data [N-1:0];
156 wire [11:0] int_data [N-1:0];
[45]157
[72]158/*
[63]159 assign osc_thrs[0] = 16'd40;
[68]160 assign osc_thrs[1] = 16'd60;
[63]161 assign osc_thrs[2] = 16'd40;
162 assign osc_thrs[3] = 16'd1650;
[72]163*/
164 wire [31:0] uwt_d1 [N-1:0];
165 wire [31:0] uwt_a1 [N-1:0];
166 wire [31:0] uwt_peak1 [N-1:0];
167 wire [31:0] uwt_d2 [N-1:0];
168 wire [31:0] uwt_a2 [N-1:0];
169 wire [31:0] uwt_peak2 [N-1:0];
170 wire [31:0] uwt_d3 [N-1:0];
171 wire [31:0] uwt_a3 [N-1:0];
172 wire [31:0] uwt_peak3 [N-1:0];
[63]173
[72]174 wire [1:0] uwt_flag1 [N-1:0];
175 wire [1:0] uwt_flag2 [N-1:0];
176 wire [1:0] uwt_flag3 [N-1:0];
[63]177
[45]178 assign adc_clk[0] = ADC_FCO;
179 assign adc_clk[1] = ADC_FCO;
[81]180 assign adc_clk[2] = ADC_FCO;
181
[63]182/*
[81]183 assign adc_clk[2] = CON_CCLK[0];
184 assign adc_data[2] = CON_C[11:0];
[63]185*/
[68]186/*
[63]187 adc_para adc_para_unit (
188 .lvds_dco(ADC_DCO),
189 .lvds_fco(ADC_FCO),
190 .para_data_ready(CON_CCLK[0]),
191 .para_data(CON_C[11:0]),
[81]192 .adc_data(adc_data[2]));
[68]193*/
[59]194/*
[54]195 wire adc_pll_clk;
196
197 adc_pll adc_pll_unit(
198 .inclk0(ADC_FCO),
199 .c0(adc_pll_clk));
200*/
[81]201/*
[59]202 wire tst_adc_clk;
203 wire [11:0] tst_adc_data;
[48]204
[59]205 test test_unit(
[63]206 .clk(CLK_50MHz),
[59]207 .tst_clk(tst_adc_clk),
208 .tst_data(tst_adc_data));
[48]209
[70]210 assign adc_clk[2] = tst_adc_clk;
211 assign adc_data[2] = tst_adc_data;
[81]212*/
[41]213/*
[38]214 altserial_flash_loader #(
215 .enable_shared_access("OFF"),
216 .enhanced_mode(1),
217 .intended_device_family("Cyclone III")) sfl_unit (
218 .noe(1'b0),
219 .asmi_access_granted(),
220 .asmi_access_request(),
221 .data0out(),
222 .dclkin(),
223 .scein(),
224 .sdoin());
[41]225*/
[72]226
[63]227 adc_lvds #(
[81]228 .size(3),
[63]229 .width(12)) adc_lvds_unit (
[41]230 .lvds_dco(ADC_DCO),
[54]231// .lvds_dco(adc_pll_clk),
[41]232 .lvds_fco(ADC_FCO),
[81]233 .lvds_d(ADC_D[2:0]),
234 .adc_data({ adc_data[2],
235 adc_data[1],
[72]236 adc_data[0] }));
237
238
239 reg [15:0] cfg_memory [31:0];
240 wire [15:0] cfg_src_data;
241 wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr;
242
243 wire cfg_polarity [N-1:0];
244 wire [11:0] cfg_baseline [N-1:0];
245 wire [11:0] cfg_hst_threshold [N-1:0];
246 wire [11:0] cfg_trg_threshold [N-1:0];
247
248 wire cfg_reset;
249
250 integer j;
251
252 always @(posedge CLK_50MHz)
253 begin
254 if (cfg_reset)
255 begin
256 for(j = 0; j <= 31; j = j + 1)
257 begin
258 cfg_memory[j] <= 16'd0;
259 end
260 end
261 else
262 begin
263 cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data;
264 end
265 end
266
[44]267 genvar i;
[72]268
[44]269 generate
[72]270 for (i = 0; i < N; i = i + 1)
[44]271 begin : MCA_CHAIN
[72]272
273 assign cfg_polarity[i] = cfg_memory[10][4*i];
274 assign cfg_baseline[i] = cfg_memory[11+i][11:0];
275 assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0];
276 assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0];
277
278 assign osc_mux_sel[i] = cfg_memory[20+i][3:0];
279 assign trg_mux_sel[i] = cfg_memory[20+i][7:4];
280
[75]281 assign hst_mux_sel[i] = cfg_memory[23+i][3:0];
282 assign bln_mux_sel[i] = cfg_memory[23+i][7:4];
283
[44]284 adc_fifo adc_fifo_unit (
[45]285 .adc_clk(adc_clk[i]),
286 .adc_data(adc_data[i]),
[59]287 .clk(CLK_50MHz),
[72]288 .data_ready(data_ready[i]),
289 .data(int_data[i]));
290
291 assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]);
292
293 uwt_bior31 #(.L(1)) uwt_1_unit (
294 .clk(CLK_50MHz),
295 .data_ready(data_ready[i]),
296 .x({20'h00000, data[i]}),
297 .d(uwt_d1[i]),
298 .a(uwt_a1[i]),
299 .peak(uwt_peak1[i]),
300 .flag(uwt_flag1[i]));
301
302 uwt_bior31 #(.L(2)) uwt_2_unit (
303 .clk(CLK_50MHz),
304 .data_ready(data_ready[i]),
305 .x(uwt_a1[i]),
306 .d(uwt_d2[i]),
307 .a(uwt_a2[i]),
308 .peak(uwt_peak2[i]),
309 .flag(uwt_flag2[i]));
310
311 uwt_bior31 #(.L(3)) uwt_3_unit (
312 .clk(CLK_50MHz),
313 .data_ready(data_ready[i]),
314 .x(uwt_a2[i]),
315 .d(uwt_d3[i]),
316 .a(uwt_a3[i]),
317 .peak(uwt_peak3[i]),
318 .flag(uwt_flag3[i]));
319
320 lpm_mux #(
[75]321 .lpm_size(5),
[72]322 .lpm_type("LPM_MUX"),
323 .lpm_width(12),
[75]324 .lpm_widths(3)) osc_mux_unit (
325 .sel(osc_mux_sel[i][2:0]),
326 .data({ bln_baseline[i],
327 uwt_a3[i][20:9],
[72]328 uwt_a2[i][17:6],
329 uwt_a1[i][14:3],
330 data[i] }),
331 .result(osc_mux_data[i]));
332
333 lpm_mux #(
[75]334 .lpm_size(5),
[72]335 .lpm_type("LPM_MUX"),
336 .lpm_width(12),
[75]337 .lpm_widths(3)) trg_mux_unit (
338 .sel(trg_mux_sel[i][2:0]),
339 .data({ bln_baseline[i],
340 uwt_a3[i][20:9],
[72]341 uwt_a2[i][17:6],
342 uwt_a1[i][14:3],
343 data[i] }),
344 .result(trg_mux_data[i]));
345
346 lpm_mux #(
347 .lpm_size(2),
348 .lpm_type("LPM_MUX"),
349 .lpm_width(13),
350 .lpm_widths(1)) hst_mux_unit (
351 .sel(hst_mux_sel[i][0]),
[80]352 .data({ {uwt_peak3[i][11:0], ana_peak_ready[i]},
[72]353 {data[i], data_ready[i]} }),
354 .result(hst_mux_data[i]));
[27]355
[72]356 lpm_mux #(
357 .lpm_size(2),
358 .lpm_type("LPM_MUX"),
359 .lpm_width(12),
360 .lpm_widths(1)) bln_mux_unit (
361 .sel(bln_mux_sel[i][0]),
362 .data({bln_baseline[i], cfg_baseline[i]}),
363 .result(bln_mux_data[i]));
364
365 baseline baseline_unit (
366 .clk(CLK_50MHz),
367 .reset(bln_reset[i]),
368 .data_ready(data_ready[i]),
369 .uwt_flag(uwt_flag3[i]),
370 .uwt_data(uwt_peak3[i]),
371 .baseline(bln_baseline[i]));
372
[44]373 analyser analyser_unit (
374 .clk(CLK_50MHz),
375 .reset(ana_reset[i]),
[72]376 .data_ready(data_ready[i]),
377 .uwt_flag(uwt_flag3[i]),
[80]378 .peak_ready(ana_peak_ready[i]));
[54]379
[72]380 assign hst_data[i] = (hst_mux_data[i][12:1] > bln_mux_data[i]) ? (hst_mux_data[i][12:1] - bln_mux_data[i]) : 12'd0;
381 assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]);
382
383 histogram #(.W(32)) histogram_unit (
[44]384 .clk(CLK_50MHz),
385 .reset(hst_reset[i]),
[72]386 .data_ready(hst_data_ready[i]),
387 .data(hst_data[i]),
[44]388 .address(hst_addr[i]),
389 .q(hst_q[i]));
[72]390
391 trigger trigger_unit (
[44]392 .clk(CLK_50MHz),
[72]393 .reset(trg_reset[i]),
394 .data_ready(data_ready[i]),
395 .data(trg_mux_data[i]),
396 .threshold(cfg_trg_threshold[i]),
397 .trigger(osc_trig[i]));
398
399
[44]400 oscilloscope oscilloscope_unit (
401 .clk(CLK_50MHz),
402 .reset(osc_reset[i]),
[72]403 .data_ready(data_ready[i]),
404 .data(osc_mux_data[i]),
405 .trigger(osc_trig[i]),
[44]406 .address(osc_addr[i]),
407 .start_address(osc_start_addr[i]),
408 .q(osc_q[i]));
409 end
410 endgenerate
[27]411
[44]412 always @*
[27]413 begin
[72]414 for (j = 0; j < N; j = j + 1)
[46]415 begin
416 osc_reset[j] = 1'b0;
417 osc_addr[j] = 10'b0;
418 hst_reset[j] = 1'b0;
419 hst_addr[j] = 12'b0;
420 end
421
[72]422 case(mux_type)
423// case({mux_type, mux_chan})
424 1'b0:
425// 3'b000, 3'b001, 3'b010, 3'b011:
[27]426 begin
[45]427 osc_reset[mux_chan] = mux_reset;
428 osc_addr[mux_chan] = mux_addr[9:0];
429 mux_max_byte = 2'd1;
430 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
[59]431 mux_max_addr = 16'd1023;
[27]432 end
[45]433
[72]434 1'b1:
435// 3'b100, 3'b101, 3'b110, 3'b011:
[27]436 begin
[45]437 hst_reset[mux_chan] = mux_reset;
438 hst_addr[mux_chan] = mux_addr[11:0];
[70]439 mux_max_byte = 2'd3;
[45]440 mux_min_addr = 16'd0;
[70]441 mux_max_addr = 16'd4095;
[27]442 end
443 endcase
444 end
[45]445
446 always @*
447 begin
[59]448 case ({mux_type, mux_byte})
449 3'b000: mux_q = osc_q[mux_chan][7:0];
450 3'b001: mux_q = osc_q[mux_chan][15:8];
[35]451
[59]452 3'b100: mux_q = hst_q[mux_chan][7:0];
453 3'b101: mux_q = hst_q[mux_chan][15:8];
454 3'b110: mux_q = hst_q[mux_chan][23:16];
[68]455 3'b111: mux_q = hst_q[mux_chan][31:24];
[45]456
457 default: mux_q = 8'd0;
458 endcase
459 end
[68]460
461 wire i2c_aclr;
462 wire i2c_wrreq;
463 wire i2c_full;
464 wire [15:0] i2c_data;
465
466 i2c_fifo i2c_unit(
467 .clk(CLK_50MHz),
468 .aclr(i2c_aclr),
469 .wrreq(i2c_wrreq),
470 .data(i2c_data),
471 .full(i2c_full),
[70]472/*
473 normal connection
[68]474 .i2c_sda(I2C_SDA),
[70]475 .i2c_scl(I2C_SCL),
[68]476
[70]477 following is a cross wire connection for EPT
478*/
479 .i2c_sda(I2C_SCL),
480 .i2c_scl(I2C_SDA));
481
[59]482 control control_unit (
483 .clk(CLK_50MHz),
[72]484 .cfg_reset(cfg_reset),
485 .cfg_src_data(cfg_memory[cfg_src_addr[4:0]]),
486 .cfg_src_addr(cfg_src_addr),
487 .cfg_dst_data(cfg_dst_data),
488 .cfg_dst_addr(cfg_dst_addr),
[59]489 .rx_empty(usb_rx_empty),
490 .tx_full(usb_tx_full),
491 .rx_data(usb_rx_data),
492 .mux_max_byte(mux_max_byte),
493 .mux_min_addr(mux_min_addr),
494 .mux_max_addr(mux_max_addr),
495 .mux_q(mux_q),
496 .mux_reset(mux_reset),
497 .mux_type(mux_type),
498 .mux_chan(mux_chan),
499 .mux_byte(mux_byte),
500 .mux_addr(mux_addr),
501 .rx_rdreq(usb_rx_rdreq),
502 .tx_wrreq(usb_tx_wrreq),
503 .tx_data(usb_tx_data),
[65]504 .ram_we(RAM_WE),
505 .ram_addr(RAM_ADDR),
506 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
[68]507 .i2c_wrreq(i2c_wrreq),
508 .i2c_data(i2c_data),
509 .i2c_full(i2c_full),
[59]510 .led(LED));
[45]511
[54]512endmodule
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