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source: trunk/MultiChannelUSB/Paella.v@ 73

Last change on this file since 73 was 72, checked in by demin, 15 years ago
testing all components together
File size: 11.8 KB

Rev	Line
[27]	1	module Paella
	2	(
	3	input wire CLK_50MHz,
	4	output wire LED,
	5
	6	inout wire [3:0] TRG,
[68]	7	inout wire I2C_SDA,
[72]	8	inout wire I2C_SCL,
[68]	9	inout wire [4:0] CON_A,
[27]	10	inout wire [15:0] CON_B,
[63]	11	input wire [12:0] CON_C,
[27]	12	input wire [1:0] CON_BCLK,
	13	input wire [1:0] CON_CCLK,
	14
	15	input wire ADC_DCO,
	16	input wire ADC_FCO,
[41]	17	input wire [2:0] ADC_D,
[27]	18
	19	output wire USB_SLRD,
	20	output wire USB_SLWR,
	21	input wire USB_IFCLK,
	22	input wire USB_FLAGA, // EMPTY flag for EP6
	23	input wire USB_FLAGB, // FULL flag for EP8
	24	input wire USB_FLAGC,
[30]	25	inout wire USB_PA0,
	26	inout wire USB_PA1,
	27	output wire USB_PA2,
	28	inout wire USB_PA3,
	29	output wire USB_PA4,
	30	output wire USB_PA5,
	31	output wire USB_PA6,
	32	inout wire USB_PA7,
[27]	33	inout wire [7:0] USB_PB,
	34
	35	output wire RAM_CLK,
	36	output wire RAM_CE1,
	37	output wire RAM_WE,
	38	output wire [19:0] RAM_ADDR,
	39	inout wire RAM_DQAP,
	40	inout wire [7:0] RAM_DQA,
	41	inout wire RAM_DQBP,
	42	inout wire [7:0] RAM_DQB
	43	);
	44
[72]	45	localparam N = 3;
	46
[27]	47	// Turn output ports off
[65]	48	/*
[27]	49	assign RAM_CLK = 1'b0;
	50	assign RAM_CE1 = 1'b0;
	51	assign RAM_WE = 1'b0;
	52	assign RAM_ADDR = 20'h00000;
[65]	53	*/
	54	assign RAM_CLK = CLK_50MHz;
	55	assign RAM_CE1 = 1'b0;
[27]	56
	57	// Turn inout ports to tri-state
	58	assign TRG = 4'bz;
[68]	59	assign CON_A = 5'bz;
[27]	60	assign CON_B = 16'bz;
[30]	61	assign USB_PA0 = 1'bz;
	62	assign USB_PA1 = 1'bz;
	63	assign USB_PA3 = 1'bz;
	64	assign USB_PA7 = 1'bz;
[65]	65	// assign RAM_DQAP = 1'bz;
	66	// assign RAM_DQA = 8'bz;
	67	// assign RAM_DQBP = 1'bz;
	68	// assign RAM_DQB = 8'bz;
[27]	69
[30]	70	assign USB_PA2 = ~usb_rden;
	71	assign USB_PA4 = usb_addr[0];
	72	assign USB_PA5 = usb_addr[1];
	73	assign USB_PA6 = ~usb_pktend;
	74
[27]	75	wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[59]	76	wire usb_aclr;
	77	wire usb_tx_wrreq, usb_rx_rdreq;
	78	wire usb_tx_full, usb_rx_empty;
	79	wire [7:0] usb_tx_data, usb_rx_data;
[27]	80	wire [1:0] usb_addr;
	81
	82	assign USB_SLRD = ~usb_rdreq;
	83	assign USB_SLWR = ~usb_wrreq;
	84
[59]	85	usb_fifo usb_unit
[27]	86	(
	87	.usb_clk(USB_IFCLK),
	88	.usb_data(USB_PB),
	89	.usb_full(~USB_FLAGB),
	90	.usb_empty(~USB_FLAGA),
	91	.usb_wrreq(usb_wrreq),
	92	.usb_rdreq(usb_rdreq),
	93	.usb_rden(usb_rden),
	94	.usb_pktend(usb_pktend),
	95	.usb_addr(usb_addr),
[34]	96
[27]	97	.clk(CLK_50MHz),
[59]	98	.aclr(usb_aclr),
[34]	99
[59]	100	.tx_full(usb_tx_full),
	101	.tx_wrreq(usb_tx_wrreq),
	102	.tx_data(usb_tx_data),
[34]	103
[59]	104	.rx_empty(usb_rx_empty),
	105	.rx_rdreq(usb_rx_rdreq),
	106	.rx_q(usb_rx_data)
[27]	107	);
	108
[72]	109	reg bln_reset [N-1:0];
	110	wire [11:0] baseline [N-1:0];
	111	wire [11:0] bln_baseline [N-1:0];
[44]	112
[72]	113	reg ana_reset [N-1:0];
	114	wire ana_peak_ready [N-1:0];
	115	wire [11:0] ana_peak [N-1:0];
[44]	116
[72]	117	reg osc_reset [N-1:0];
	118	reg [9:0] osc_addr [N-1:0];
	119	wire [9:0] osc_start_addr [N-1:0];
	120	wire [15:0] osc_q [N-1:0];
	121	wire osc_trig [N-1:0];
[27]	122
[72]	123	wire [3:0] osc_mux_sel [N-1:0];
	124	wire [11:0] osc_mux_data [N-1:0];
	125
	126	wire trg_reset [N-1:0];
	127	wire [3:0] trg_mux_sel [N-1:0];
	128	wire [11:0] trg_mux_data [N-1:0];
	129	wire [11:0] trg_thrs [N-1:0];
	130
	131	reg hst_reset [N-1:0];
	132	reg [11:0] hst_addr [N-1:0];
	133	wire hst_data_ready [N-1:0];
	134	wire [11:0] hst_data [N-1:0];
	135	wire [31:0] hst_q [N-1:0];
	136
	137
	138	wire [3:0] hst_mux_sel [N-1:0];
	139	wire [12:0] hst_mux_data [N-1:0];
	140
	141	wire [3:0] bln_mux_sel [N-1:0];
	142	wire [11:0] bln_mux_data [N-1:0];
	143
[59]	144	wire mux_reset, mux_type;
	145	wire [1:0] mux_chan, mux_byte;
	146	wire [15:0] mux_addr;
	147
[45]	148	reg [7:0] mux_q;
[59]	149	reg [1:0] mux_max_byte;
	150	reg [15:0] mux_min_addr, mux_max_addr;
[44]	151
[72]	152	wire adc_clk [N-1:0];
	153	wire [11:0] adc_data [N-1:0];
[41]	154
[72]	155	wire data_ready [N-1:0];
	156	wire [11:0] data [N-1:0];
	157	wire [11:0] int_data [N-1:0];
[45]	158
[72]	159	/*
[63]	160	assign osc_thrs[0] = 16'd40;
[68]	161	assign osc_thrs[1] = 16'd60;
[63]	162	assign osc_thrs[2] = 16'd40;
	163	assign osc_thrs[3] = 16'd1650;
[72]	164	*/
	165	wire [31:0] uwt_d1 [N-1:0];
	166	wire [31:0] uwt_a1 [N-1:0];
	167	wire [31:0] uwt_peak1 [N-1:0];
	168	wire [31:0] uwt_d2 [N-1:0];
	169	wire [31:0] uwt_a2 [N-1:0];
	170	wire [31:0] uwt_peak2 [N-1:0];
	171	wire [31:0] uwt_d3 [N-1:0];
	172	wire [31:0] uwt_a3 [N-1:0];
	173	wire [31:0] uwt_peak3 [N-1:0];
[63]	174
[72]	175	wire [1:0] uwt_flag1 [N-1:0];
	176	wire [1:0] uwt_flag2 [N-1:0];
	177	wire [1:0] uwt_flag3 [N-1:0];
[63]	178
[45]	179	assign adc_clk[0] = ADC_FCO;
	180	assign adc_clk[1] = ADC_FCO;
[70]	181	// assign adc_clk[2] = ADC_FCO;
[72]	182	/*
[63]	183	assign adc_clk[3] = ADC_FCO;
[72]	184	*/
[63]	185	/*
	186	assign adc_clk[3] = CON_CCLK[0];
	187	assign adc_data[3] = CON_C[11:0];
	188	*/
[68]	189	/*
[63]	190	adc_para adc_para_unit (
	191	.lvds_dco(ADC_DCO),
	192	.lvds_fco(ADC_FCO),
	193	.para_data_ready(CON_CCLK[0]),
	194	.para_data(CON_C[11:0]),
	195	.adc_data(adc_data[3]));
[68]	196	*/
[59]	197	/*
[54]	198	wire adc_pll_clk;
	199
	200	adc_pll adc_pll_unit(
	201	.inclk0(ADC_FCO),
	202	.c0(adc_pll_clk));
	203	*/
[70]	204
[59]	205	wire tst_adc_clk;
	206	wire [11:0] tst_adc_data;
[48]	207
[59]	208	test test_unit(
[63]	209	.clk(CLK_50MHz),
[59]	210	.tst_clk(tst_adc_clk),
	211	.tst_data(tst_adc_data));
[48]	212
[70]	213	assign adc_clk[2] = tst_adc_clk;
	214	assign adc_data[2] = tst_adc_data;
	215
[41]	216	/*
[38]	217	altserial_flash_loader #(
	218	.enable_shared_access("OFF"),
	219	.enhanced_mode(1),
	220	.intended_device_family("Cyclone III")) sfl_unit (
	221	.noe(1'b0),
	222	.asmi_access_granted(),
	223	.asmi_access_request(),
	224	.data0out(),
	225	.dclkin(),
	226	.scein(),
	227	.sdoin());
[41]	228	*/
[72]	229
[63]	230	adc_lvds #(
[72]	231	.size(2),
[63]	232	.width(12)) adc_lvds_unit (
[41]	233	.lvds_dco(ADC_DCO),
[54]	234	// .lvds_dco(adc_pll_clk),
[41]	235	.lvds_fco(ADC_FCO),
[72]	236	.lvds_d(ADC_D[1:0]),
	237	.adc_data({ adc_data[1],
	238	adc_data[0] }));
	239
	240
	241	reg [15:0] cfg_memory [31:0];
	242	wire [15:0] cfg_src_data;
	243	wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr;
	244
	245	wire cfg_polarity [N-1:0];
	246	wire [11:0] cfg_baseline [N-1:0];
	247	wire [11:0] cfg_hst_threshold [N-1:0];
	248	wire [11:0] cfg_trg_threshold [N-1:0];
	249
	250	wire cfg_reset;
	251
	252	integer j;
	253
	254	always @(posedge CLK_50MHz)
	255	begin
	256	if (cfg_reset)
	257	begin
	258	for(j = 0; j <= 31; j = j + 1)
	259	begin
	260	cfg_memory[j] <= 16'd0;
	261	end
	262	end
	263	else
	264	begin
	265	cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data;
	266	end
	267	end
	268
[44]	269	genvar i;
[72]	270
[44]	271	generate
[72]	272	for (i = 0; i < N; i = i + 1)
[44]	273	begin : MCA_CHAIN
[72]	274
	275	assign cfg_polarity[i] = cfg_memory[10][4*i];
	276	assign cfg_baseline[i] = cfg_memory[11+i][11:0];
	277	assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0];
	278	assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0];
	279
	280	assign osc_mux_sel[i] = cfg_memory[20+i][3:0];
	281	assign trg_mux_sel[i] = cfg_memory[20+i][7:4];
	282	assign hst_mux_sel[i] = cfg_memory[20+i][11:8];
	283	assign bln_mux_sel[i] = cfg_memory[20+i][15:12];
	284
[44]	285	adc_fifo adc_fifo_unit (
[45]	286	.adc_clk(adc_clk[i]),
	287	.adc_data(adc_data[i]),
[59]	288	.clk(CLK_50MHz),
[72]	289	.data_ready(data_ready[i]),
	290	.data(int_data[i]));
	291
	292	assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]);
	293
	294	uwt_bior31 #(.L(1)) uwt_1_unit (
	295	.clk(CLK_50MHz),
	296	.data_ready(data_ready[i]),
	297	.x({20'h00000, data[i]}),
	298	.d(uwt_d1[i]),
	299	.a(uwt_a1[i]),
	300	.peak(uwt_peak1[i]),
	301	.flag(uwt_flag1[i]));
	302
	303	uwt_bior31 #(.L(2)) uwt_2_unit (
	304	.clk(CLK_50MHz),
	305	.data_ready(data_ready[i]),
	306	.x(uwt_a1[i]),
	307	.d(uwt_d2[i]),
	308	.a(uwt_a2[i]),
	309	.peak(uwt_peak2[i]),
	310	.flag(uwt_flag2[i]));
	311
	312	uwt_bior31 #(.L(3)) uwt_3_unit (
	313	.clk(CLK_50MHz),
	314	.data_ready(data_ready[i]),
	315	.x(uwt_a2[i]),
	316	.d(uwt_d3[i]),
	317	.a(uwt_a3[i]),
	318	.peak(uwt_peak3[i]),
	319	.flag(uwt_flag3[i]));
	320
	321	lpm_mux #(
	322	.lpm_size(4),
	323	.lpm_type("LPM_MUX"),
	324	.lpm_width(12),
	325	.lpm_widths(2)) osc_mux_unit (
	326	.sel(osc_mux_sel[i][1:0]),
	327	.data({ uwt_a3[i][20:9],
	328	uwt_a2[i][17:6],
	329	uwt_a1[i][14:3],
	330	data[i] }),
	331	.result(osc_mux_data[i]));
	332
	333	lpm_mux #(
	334	.lpm_size(4),
	335	.lpm_type("LPM_MUX"),
	336	.lpm_width(12),
	337	.lpm_widths(2)) trg_mux_unit (
	338	.sel(trg_mux_sel[i][1:0]),
	339	.data({ uwt_a3[i][20:9],
	340	uwt_a2[i][17:6],
	341	uwt_a1[i][14:3],
	342	data[i] }),
	343	.result(trg_mux_data[i]));
	344
	345	lpm_mux #(
	346	.lpm_size(2),
	347	.lpm_type("LPM_MUX"),
	348	.lpm_width(13),
	349	.lpm_widths(1)) hst_mux_unit (
	350	.sel(hst_mux_sel[i][0]),
	351	.data({ {ana_peak[i], ana_peak_ready[i]},
	352	{data[i], data_ready[i]} }),
	353	.result(hst_mux_data[i]));
[27]	354
[72]	355	lpm_mux #(
	356	.lpm_size(2),
	357	.lpm_type("LPM_MUX"),
	358	.lpm_width(12),
	359	.lpm_widths(1)) bln_mux_unit (
	360	.sel(bln_mux_sel[i][0]),
	361	.data({bln_baseline[i], cfg_baseline[i]}),
	362	.result(bln_mux_data[i]));
	363
	364	baseline baseline_unit (
	365	.clk(CLK_50MHz),
	366	.reset(bln_reset[i]),
	367	.data_ready(data_ready[i]),
	368	.uwt_flag(uwt_flag3[i]),
	369	.uwt_data(uwt_peak3[i]),
	370	.baseline(bln_baseline[i]));
	371
[44]	372	analyser analyser_unit (
	373	.clk(CLK_50MHz),
	374	.reset(ana_reset[i]),
[72]	375	.data_ready(data_ready[i]),
	376	.uwt_flag(uwt_flag3[i]),
	377	.uwt_data(uwt_peak3[i]),
[44]	378	.peak_ready(ana_peak_ready[i]),
	379	.peak(ana_peak[i]));
[54]	380
[72]	381	assign hst_data[i] = (hst_mux_data[i][12:1] > bln_mux_data[i]) ? (hst_mux_data[i][12:1] - bln_mux_data[i]) : 12'd0;
	382	assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]);
	383
	384	histogram #(.W(32)) histogram_unit (
[44]	385	.clk(CLK_50MHz),
	386	.reset(hst_reset[i]),
[72]	387	.data_ready(hst_data_ready[i]),
	388	.data(hst_data[i]),
[44]	389	.address(hst_addr[i]),
	390	.q(hst_q[i]));
[72]	391
	392	trigger trigger_unit (
[44]	393	.clk(CLK_50MHz),
[72]	394	.reset(trg_reset[i]),
	395	.data_ready(data_ready[i]),
	396	.data(trg_mux_data[i]),
	397	.threshold(cfg_trg_threshold[i]),
	398	.trigger(osc_trig[i]));
	399
	400
[44]	401	oscilloscope oscilloscope_unit (
	402	.clk(CLK_50MHz),
	403	.reset(osc_reset[i]),
[72]	404	.data_ready(data_ready[i]),
	405	.data(osc_mux_data[i]),
	406	.trigger(osc_trig[i]),
[44]	407	.address(osc_addr[i]),
	408	.start_address(osc_start_addr[i]),
	409	.q(osc_q[i]));
	410	end
	411	endgenerate
[27]	412
[44]	413	always @*
[27]	414	begin
[72]	415	for (j = 0; j < N; j = j + 1)
[46]	416	begin
	417	osc_reset[j] = 1'b0;
	418	osc_addr[j] = 10'b0;
	419	hst_reset[j] = 1'b0;
	420	hst_addr[j] = 12'b0;
	421	end
	422
[72]	423	case(mux_type)
	424	// case({mux_type, mux_chan})
	425	1'b0:
	426	// 3'b000, 3'b001, 3'b010, 3'b011:
[27]	427	begin
[45]	428	osc_reset[mux_chan] = mux_reset;
	429	osc_addr[mux_chan] = mux_addr[9:0];
	430	mux_max_byte = 2'd1;
	431	mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
[59]	432	mux_max_addr = 16'd1023;
[27]	433	end
[45]	434
[72]	435	1'b1:
	436	// 3'b100, 3'b101, 3'b110, 3'b011:
[27]	437	begin
[45]	438	hst_reset[mux_chan] = mux_reset;
	439	hst_addr[mux_chan] = mux_addr[11:0];
[70]	440	mux_max_byte = 2'd3;
[45]	441	mux_min_addr = 16'd0;
[70]	442	mux_max_addr = 16'd4095;
[27]	443	end
	444	endcase
	445	end
[45]	446
	447	always @*
	448	begin
[59]	449	case ({mux_type, mux_byte})
	450	3'b000: mux_q = osc_q[mux_chan][7:0];
	451	3'b001: mux_q = osc_q[mux_chan][15:8];
[35]	452
[59]	453	3'b100: mux_q = hst_q[mux_chan][7:0];
	454	3'b101: mux_q = hst_q[mux_chan][15:8];
	455	3'b110: mux_q = hst_q[mux_chan][23:16];
[68]	456	3'b111: mux_q = hst_q[mux_chan][31:24];
[45]	457
	458	default: mux_q = 8'd0;
	459	endcase
	460	end
[68]	461
	462	wire i2c_aclr;
	463	wire i2c_wrreq;
	464	wire i2c_full;
	465	wire [15:0] i2c_data;
	466
	467	i2c_fifo i2c_unit(
	468	.clk(CLK_50MHz),
	469	.aclr(i2c_aclr),
	470	.wrreq(i2c_wrreq),
	471	.data(i2c_data),
	472	.full(i2c_full),
[70]	473	/*
	474	normal connection
[68]	475	.i2c_sda(I2C_SDA),
[70]	476	.i2c_scl(I2C_SCL),
[68]	477
[70]	478	following is a cross wire connection for EPT
	479	*/
	480	.i2c_sda(I2C_SCL),
	481	.i2c_scl(I2C_SDA));
	482
[59]	483	control control_unit (
	484	.clk(CLK_50MHz),
[72]	485	.cfg_reset(cfg_reset),
	486	.cfg_src_data(cfg_memory[cfg_src_addr[4:0]]),
	487	.cfg_src_addr(cfg_src_addr),
	488	.cfg_dst_data(cfg_dst_data),
	489	.cfg_dst_addr(cfg_dst_addr),
[59]	490	.rx_empty(usb_rx_empty),
	491	.tx_full(usb_tx_full),
	492	.rx_data(usb_rx_data),
	493	.mux_max_byte(mux_max_byte),
	494	.mux_min_addr(mux_min_addr),
	495	.mux_max_addr(mux_max_addr),
	496	.mux_q(mux_q),
	497	.mux_reset(mux_reset),
	498	.mux_type(mux_type),
	499	.mux_chan(mux_chan),
	500	.mux_byte(mux_byte),
	501	.mux_addr(mux_addr),
	502	.rx_rdreq(usb_rx_rdreq),
	503	.tx_wrreq(usb_tx_wrreq),
	504	.tx_data(usb_tx_data),
[65]	505	.ram_we(RAM_WE),
	506	.ram_addr(RAM_ADDR),
	507	.ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
[68]	508	.i2c_wrreq(i2c_wrreq),
	509	.i2c_data(i2c_data),
	510	.i2c_full(i2c_full),
[59]	511	.led(LED));
[45]	512
[54]	513	endmodule

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