source: trunk/MultiChannelUSB/Paella.v@ 66

Last change on this file since 66 was 65, checked in by demin, 15 years ago

start testing SRAM
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[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
[63]9 input wire [12:0] CON_C,
[27]10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
[41]15 input wire [2:0] ADC_D,
[27]16
17 output wire USB_SLRD,
18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 input wire USB_FLAGC,
[30]23 inout wire USB_PA0,
24 inout wire USB_PA1,
25 output wire USB_PA2,
26 inout wire USB_PA3,
27 output wire USB_PA4,
28 output wire USB_PA5,
29 output wire USB_PA6,
30 inout wire USB_PA7,
[27]31 inout wire [7:0] USB_PB,
32
33 output wire RAM_CLK,
34 output wire RAM_CE1,
35 output wire RAM_WE,
36 output wire [19:0] RAM_ADDR,
37 inout wire RAM_DQAP,
38 inout wire [7:0] RAM_DQA,
39 inout wire RAM_DQBP,
40 inout wire [7:0] RAM_DQB
41 );
42
43 // Turn output ports off
[65]44/*
[27]45 assign RAM_CLK = 1'b0;
46 assign RAM_CE1 = 1'b0;
47 assign RAM_WE = 1'b0;
48 assign RAM_ADDR = 20'h00000;
[65]49*/
50 assign RAM_CLK = CLK_50MHz;
51 assign RAM_CE1 = 1'b0;
[27]52
53 // Turn inout ports to tri-state
54 assign TRG = 4'bz;
55 assign CON_A = 7'bz;
56 assign CON_B = 16'bz;
[30]57 assign USB_PA0 = 1'bz;
58 assign USB_PA1 = 1'bz;
59 assign USB_PA3 = 1'bz;
60 assign USB_PA7 = 1'bz;
[65]61// assign RAM_DQAP = 1'bz;
62// assign RAM_DQA = 8'bz;
63// assign RAM_DQBP = 1'bz;
64// assign RAM_DQB = 8'bz;
[27]65
[30]66 assign USB_PA2 = ~usb_rden;
67 assign USB_PA4 = usb_addr[0];
68 assign USB_PA5 = usb_addr[1];
69 assign USB_PA6 = ~usb_pktend;
70
[27]71 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[59]72 wire usb_aclr;
73 wire usb_tx_wrreq, usb_rx_rdreq;
74 wire usb_tx_full, usb_rx_empty;
75 wire [7:0] usb_tx_data, usb_rx_data;
[27]76 wire [1:0] usb_addr;
77
78 assign USB_SLRD = ~usb_rdreq;
79 assign USB_SLWR = ~usb_wrreq;
80
[59]81 usb_fifo usb_unit
[27]82 (
83 .usb_clk(USB_IFCLK),
84 .usb_data(USB_PB),
85 .usb_full(~USB_FLAGB),
86 .usb_empty(~USB_FLAGA),
87 .usb_wrreq(usb_wrreq),
88 .usb_rdreq(usb_rdreq),
89 .usb_rden(usb_rden),
90 .usb_pktend(usb_pktend),
91 .usb_addr(usb_addr),
[34]92
[27]93 .clk(CLK_50MHz),
[59]94 .aclr(usb_aclr),
[34]95
[59]96 .tx_full(usb_tx_full),
97 .tx_wrreq(usb_tx_wrreq),
98 .tx_data(usb_tx_data),
[34]99
[59]100 .rx_empty(usb_rx_empty),
101 .rx_rdreq(usb_rx_rdreq),
102 .rx_q(usb_rx_data)
[27]103 );
104
[45]105 reg ana_reset [3:0];
106 wire ana_peak_ready [3:0];
107 wire [11:0] ana_peak [3:0];
[44]108
[45]109 reg osc_reset [3:0];
[59]110 reg [9:0] osc_addr [3:0];
[45]111 wire [9:0] osc_start_addr [3:0];
112 wire [15:0] osc_q [3:0];
[44]113
[45]114 reg hst_reset [3:0];
115 reg [11:0] hst_addr [3:0];
116 wire [23:0] hst_q [3:0];
[27]117
[59]118 wire mux_reset, mux_type;
119 wire [1:0] mux_chan, mux_byte;
120 wire [15:0] mux_addr;
121
[45]122 reg [7:0] mux_q;
[59]123 reg [1:0] mux_max_byte;
124 reg [15:0] mux_min_addr, mux_max_addr;
[44]125
[45]126 wire adc_clk [3:0];
127 wire adc_data_ready [3:0];
128 wire [11:0] adc_data [3:0];
[41]129
[45]130 wire [11:0] raw_data [3:0];
131 wire [11:0] uwt_data [3:0];
132 wire [1:0] uwt_flag [3:0];
133
[63]134 wire [16:0] osc_thrs [3:0];
135 wire adc_pola [3:0];
136
137 assign osc_thrs[0] = 16'd40;
138 assign osc_thrs[1] = 16'd300;
139 assign osc_thrs[2] = 16'd40;
140 assign osc_thrs[3] = 16'd1650;
141
142 assign adc_pola[0] = 1'b1;
143 assign adc_pola[1] = 1'b1;
144 assign adc_pola[2] = 1'b1;
145 assign adc_pola[3] = 1'b0;
146
[45]147 assign adc_clk[0] = ADC_FCO;
148 assign adc_clk[1] = ADC_FCO;
149 assign adc_clk[2] = ADC_FCO;
[63]150
151 assign adc_clk[3] = ADC_FCO;
152/*
153 assign adc_clk[3] = CON_CCLK[0];
154 assign adc_data[3] = CON_C[11:0];
155*/
156 adc_para adc_para_unit (
157 .lvds_dco(ADC_DCO),
158 .lvds_fco(ADC_FCO),
159 .para_data_ready(CON_CCLK[0]),
160 .para_data(CON_C[11:0]),
161 .adc_data(adc_data[3]));
162
[59]163/*
[54]164 wire adc_pll_clk;
165
166 adc_pll adc_pll_unit(
167 .inclk0(ADC_FCO),
168 .c0(adc_pll_clk));
169*/
[59]170/*
171 wire tst_adc_clk;
172 wire [11:0] tst_adc_data;
[48]173
[59]174 test test_unit(
[63]175 .clk(CLK_50MHz),
[59]176 .tst_clk(tst_adc_clk),
177 .tst_data(tst_adc_data));
[48]178
[59]179 assign adc_clk[3] = tst_adc_clk;
180 assign adc_data[3] = tst_adc_data;
181*/
[41]182/*
[38]183 altserial_flash_loader #(
184 .enable_shared_access("OFF"),
185 .enhanced_mode(1),
186 .intended_device_family("Cyclone III")) sfl_unit (
187 .noe(1'b0),
188 .asmi_access_granted(),
189 .asmi_access_request(),
190 .data0out(),
191 .dclkin(),
192 .scein(),
193 .sdoin());
[41]194*/
[54]195
[63]196 adc_lvds #(
197 .size(3),
198 .width(12)) adc_lvds_unit (
[41]199 .lvds_dco(ADC_DCO),
[54]200// .lvds_dco(adc_pll_clk),
[41]201 .lvds_fco(ADC_FCO),
202 .lvds_d(ADC_D),
[63]203 .adc_data({ adc_data[0],
204 adc_data[1],
205 adc_data[2]}));
[44]206
207 genvar i;
208 generate
[63]209 for (i = 1; i < 4; i = i + 1)
[44]210 begin : MCA_CHAIN
211 adc_fifo adc_fifo_unit (
[45]212 .adc_clk(adc_clk[i]),
213 .adc_data(adc_data[i]),
[63]214 .polarity(adc_pola[i]),
[59]215 .clk(CLK_50MHz),
[44]216 .ready(adc_data_ready[i]),
217 .raw_data(raw_data[i]),
218 .uwt_data({uwt_flag[i], uwt_data[i]}));
[27]219
[44]220 analyser analyser_unit (
221 .clk(CLK_50MHz),
222 .reset(ana_reset[i]),
223 .data_ready(adc_data_ready[i]),
224 .uwt_flag(uwt_flag[i]),
225 .uwt_data(uwt_data[i]),
[54]226 .threshold(12'd10),
[44]227 .peak_ready(ana_peak_ready[i]),
228 .peak(ana_peak[i]));
[54]229
[44]230 histogram histogram_unit (
231 .clk(CLK_50MHz),
232 .reset(hst_reset[i]),
233 .data_ready(adc_data_ready[i]),
[63]234 .data(raw_data[i]),
235// .data(uwt_data[i]),
[44]236 .address(hst_addr[i]),
237 .q(hst_q[i]));
[54]238/*
[44]239 histogram histogram_unit (
240 .clk(CLK_50MHz),
241 .reset(hst_reset[i]),
242 .data_ready(ana_peak_ready[i]),
243 .data(ana_peak[i]),
244 .address(hst_addr[i]),
245 .q(hst_q[i]));
[54]246*/
[44]247 oscilloscope oscilloscope_unit (
248 .clk(CLK_50MHz),
249 .reset(osc_reset[i]),
250 .data_ready(adc_data_ready[i]),
251 .raw_data(raw_data[i]),
252 .uwt_data(uwt_data[i]),
[63]253 .threshold(osc_thrs[i]),
[44]254 .address(osc_addr[i]),
255 .start_address(osc_start_addr[i]),
256 .q(osc_q[i]));
257 end
258 endgenerate
[27]259
[46]260 integer j;
261
[44]262 always @*
[27]263 begin
[46]264 for (j = 0; j < 4; j = j + 1)
265 begin
266 osc_reset[j] = 1'b0;
267 osc_addr[j] = 10'b0;
268 hst_reset[j] = 1'b0;
269 hst_addr[j] = 12'b0;
270 end
271
[59]272 case({mux_type, mux_chan})
[45]273 3'b000, 3'b001, 3'b010, 3'b011:
[27]274 begin
[45]275 osc_reset[mux_chan] = mux_reset;
276 osc_addr[mux_chan] = mux_addr[9:0];
277 mux_max_byte = 2'd1;
278 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
[59]279 mux_max_addr = 16'd1023;
[27]280 end
[45]281
282 3'b100, 3'b101, 3'b110, 3'b111:
[27]283 begin
[45]284 hst_reset[mux_chan] = mux_reset;
285 hst_addr[mux_chan] = mux_addr[11:0];
286 mux_max_byte = 2'd2;
287 mux_min_addr = 16'd0;
[59]288 mux_max_addr = 16'd4095;
[27]289 end
290 endcase
291 end
[45]292
293 always @*
294 begin
[59]295 case ({mux_type, mux_byte})
296 3'b000: mux_q = osc_q[mux_chan][7:0];
297 3'b001: mux_q = osc_q[mux_chan][15:8];
[35]298
[59]299 3'b100: mux_q = hst_q[mux_chan][7:0];
300 3'b101: mux_q = hst_q[mux_chan][15:8];
301 3'b110: mux_q = hst_q[mux_chan][23:16];
[45]302
303 default: mux_q = 8'd0;
304 endcase
305 end
[65]306
[59]307 control control_unit (
308 .clk(CLK_50MHz),
309 .rx_empty(usb_rx_empty),
310 .tx_full(usb_tx_full),
311 .rx_data(usb_rx_data),
312 .mux_max_byte(mux_max_byte),
313 .mux_min_addr(mux_min_addr),
314 .mux_max_addr(mux_max_addr),
315 .mux_q(mux_q),
316 .mux_reset(mux_reset),
317 .mux_type(mux_type),
318 .mux_chan(mux_chan),
319 .mux_byte(mux_byte),
320 .mux_addr(mux_addr),
321 .rx_rdreq(usb_rx_rdreq),
322 .tx_wrreq(usb_tx_wrreq),
323 .tx_data(usb_tx_data),
[65]324 .ram_we(RAM_WE),
325 .ram_addr(RAM_ADDR),
326 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
[59]327 .led(LED));
[45]328
[54]329endmodule
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