source: trunk/MultiChannelUSB/Paella.v@ 63

Last change on this file since 63 was 63, checked in by demin, 15 years ago

add parameters for number of channels and channel resolution
File size: 7.2 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 input wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
15 input wire [2:0] ADC_D,
16
17 output wire USB_SLRD,
18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 input wire USB_FLAGC,
23 inout wire USB_PA0,
24 inout wire USB_PA1,
25 output wire USB_PA2,
26 inout wire USB_PA3,
27 output wire USB_PA4,
28 output wire USB_PA5,
29 output wire USB_PA6,
30 inout wire USB_PA7,
31 inout wire [7:0] USB_PB,
32
33 output wire RAM_CLK,
34 output wire RAM_CE1,
35 output wire RAM_WE,
36 output wire [19:0] RAM_ADDR,
37 inout wire RAM_DQAP,
38 inout wire [7:0] RAM_DQA,
39 inout wire RAM_DQBP,
40 inout wire [7:0] RAM_DQB
41 );
42
43 // Turn output ports off
44 assign RAM_CLK = 1'b0;
45 assign RAM_CE1 = 1'b0;
46 assign RAM_WE = 1'b0;
47 assign RAM_ADDR = 20'h00000;
48
49 // Turn inout ports to tri-state
50 assign TRG = 4'bz;
51 assign CON_A = 7'bz;
52 assign CON_B = 16'bz;
53 assign USB_PA0 = 1'bz;
54 assign USB_PA1 = 1'bz;
55 assign USB_PA3 = 1'bz;
56 assign USB_PA7 = 1'bz;
57 assign RAM_DQAP = 1'bz;
58 assign RAM_DQA = 8'bz;
59 assign RAM_DQBP = 1'bz;
60 assign RAM_DQB = 8'bz;
61
62 assign USB_PA2 = ~usb_rden;
63 assign USB_PA4 = usb_addr[0];
64 assign USB_PA5 = usb_addr[1];
65 assign USB_PA6 = ~usb_pktend;
66
67 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
68 wire usb_aclr;
69 wire usb_tx_wrreq, usb_rx_rdreq;
70 wire usb_tx_full, usb_rx_empty;
71 wire [7:0] usb_tx_data, usb_rx_data;
72 wire [1:0] usb_addr;
73
74 assign USB_SLRD = ~usb_rdreq;
75 assign USB_SLWR = ~usb_wrreq;
76
77 usb_fifo usb_unit
78 (
79 .usb_clk(USB_IFCLK),
80 .usb_data(USB_PB),
81 .usb_full(~USB_FLAGB),
82 .usb_empty(~USB_FLAGA),
83 .usb_wrreq(usb_wrreq),
84 .usb_rdreq(usb_rdreq),
85 .usb_rden(usb_rden),
86 .usb_pktend(usb_pktend),
87 .usb_addr(usb_addr),
88
89 .clk(CLK_50MHz),
90 .aclr(usb_aclr),
91
92 .tx_full(usb_tx_full),
93 .tx_wrreq(usb_tx_wrreq),
94 .tx_data(usb_tx_data),
95
96 .rx_empty(usb_rx_empty),
97 .rx_rdreq(usb_rx_rdreq),
98 .rx_q(usb_rx_data)
99 );
100
101 reg ana_reset [3:0];
102 wire ana_peak_ready [3:0];
103 wire [11:0] ana_peak [3:0];
104
105 reg osc_reset [3:0];
106 reg [9:0] osc_addr [3:0];
107 wire [9:0] osc_start_addr [3:0];
108 wire [15:0] osc_q [3:0];
109
110 reg hst_reset [3:0];
111 reg [11:0] hst_addr [3:0];
112 wire [23:0] hst_q [3:0];
113
114 wire mux_reset, mux_type;
115 wire [1:0] mux_chan, mux_byte;
116 wire [15:0] mux_addr;
117
118 reg [7:0] mux_q;
119 reg [1:0] mux_max_byte;
120 reg [15:0] mux_min_addr, mux_max_addr;
121
122 wire adc_clk [3:0];
123 wire adc_data_ready [3:0];
124 wire [11:0] adc_data [3:0];
125
126 wire [11:0] raw_data [3:0];
127 wire [11:0] uwt_data [3:0];
128 wire [1:0] uwt_flag [3:0];
129
130 wire [16:0] osc_thrs [3:0];
131 wire adc_pola [3:0];
132
133 assign osc_thrs[0] = 16'd40;
134 assign osc_thrs[1] = 16'd300;
135 assign osc_thrs[2] = 16'd40;
136 assign osc_thrs[3] = 16'd1650;
137
138 assign adc_pola[0] = 1'b1;
139 assign adc_pola[1] = 1'b1;
140 assign adc_pola[2] = 1'b1;
141 assign adc_pola[3] = 1'b0;
142
143 assign adc_clk[0] = ADC_FCO;
144 assign adc_clk[1] = ADC_FCO;
145 assign adc_clk[2] = ADC_FCO;
146
147 assign adc_clk[3] = ADC_FCO;
148/*
149 assign adc_clk[3] = CON_CCLK[0];
150 assign adc_data[3] = CON_C[11:0];
151*/
152 adc_para adc_para_unit (
153 .lvds_dco(ADC_DCO),
154 .lvds_fco(ADC_FCO),
155 .para_data_ready(CON_CCLK[0]),
156 .para_data(CON_C[11:0]),
157 .adc_data(adc_data[3]));
158
159/*
160 wire adc_pll_clk;
161
162 adc_pll adc_pll_unit(
163 .inclk0(ADC_FCO),
164 .c0(adc_pll_clk));
165*/
166/*
167 wire tst_adc_clk;
168 wire [11:0] tst_adc_data;
169
170 test test_unit(
171 .clk(CLK_50MHz),
172 .tst_clk(tst_adc_clk),
173 .tst_data(tst_adc_data));
174
175 assign adc_clk[3] = tst_adc_clk;
176 assign adc_data[3] = tst_adc_data;
177*/
178/*
179 altserial_flash_loader #(
180 .enable_shared_access("OFF"),
181 .enhanced_mode(1),
182 .intended_device_family("Cyclone III")) sfl_unit (
183 .noe(1'b0),
184 .asmi_access_granted(),
185 .asmi_access_request(),
186 .data0out(),
187 .dclkin(),
188 .scein(),
189 .sdoin());
190*/
191
192 adc_lvds #(
193 .size(3),
194 .width(12)) adc_lvds_unit (
195 .lvds_dco(ADC_DCO),
196// .lvds_dco(adc_pll_clk),
197 .lvds_fco(ADC_FCO),
198 .lvds_d(ADC_D),
199 .adc_data({ adc_data[0],
200 adc_data[1],
201 adc_data[2]}));
202
203 genvar i;
204 generate
205 for (i = 1; i < 4; i = i + 1)
206 begin : MCA_CHAIN
207 adc_fifo adc_fifo_unit (
208 .adc_clk(adc_clk[i]),
209 .adc_data(adc_data[i]),
210 .polarity(adc_pola[i]),
211 .clk(CLK_50MHz),
212 .ready(adc_data_ready[i]),
213 .raw_data(raw_data[i]),
214 .uwt_data({uwt_flag[i], uwt_data[i]}));
215
216 analyser analyser_unit (
217 .clk(CLK_50MHz),
218 .reset(ana_reset[i]),
219 .data_ready(adc_data_ready[i]),
220 .uwt_flag(uwt_flag[i]),
221 .uwt_data(uwt_data[i]),
222 .threshold(12'd10),
223 .peak_ready(ana_peak_ready[i]),
224 .peak(ana_peak[i]));
225
226 histogram histogram_unit (
227 .clk(CLK_50MHz),
228 .reset(hst_reset[i]),
229 .data_ready(adc_data_ready[i]),
230 .data(raw_data[i]),
231// .data(uwt_data[i]),
232 .address(hst_addr[i]),
233 .q(hst_q[i]));
234/*
235 histogram histogram_unit (
236 .clk(CLK_50MHz),
237 .reset(hst_reset[i]),
238 .data_ready(ana_peak_ready[i]),
239 .data(ana_peak[i]),
240 .address(hst_addr[i]),
241 .q(hst_q[i]));
242*/
243 oscilloscope oscilloscope_unit (
244 .clk(CLK_50MHz),
245 .reset(osc_reset[i]),
246 .data_ready(adc_data_ready[i]),
247 .raw_data(raw_data[i]),
248 .uwt_data(uwt_data[i]),
249 .threshold(osc_thrs[i]),
250 .address(osc_addr[i]),
251 .start_address(osc_start_addr[i]),
252 .q(osc_q[i]));
253 end
254 endgenerate
255
256 integer j;
257
258 always @*
259 begin
260 for (j = 0; j < 4; j = j + 1)
261 begin
262 osc_reset[j] = 1'b0;
263 osc_addr[j] = 10'b0;
264 hst_reset[j] = 1'b0;
265 hst_addr[j] = 12'b0;
266 end
267
268 case({mux_type, mux_chan})
269 3'b000, 3'b001, 3'b010, 3'b011:
270 begin
271 osc_reset[mux_chan] = mux_reset;
272 osc_addr[mux_chan] = mux_addr[9:0];
273 mux_max_byte = 2'd1;
274 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
275 mux_max_addr = 16'd1023;
276 end
277
278 3'b100, 3'b101, 3'b110, 3'b111:
279 begin
280 hst_reset[mux_chan] = mux_reset;
281 hst_addr[mux_chan] = mux_addr[11:0];
282 mux_max_byte = 2'd2;
283 mux_min_addr = 16'd0;
284 mux_max_addr = 16'd4095;
285 end
286 endcase
287 end
288
289 always @*
290 begin
291 case ({mux_type, mux_byte})
292 3'b000: mux_q = osc_q[mux_chan][7:0];
293 3'b001: mux_q = osc_q[mux_chan][15:8];
294
295 3'b100: mux_q = hst_q[mux_chan][7:0];
296 3'b101: mux_q = hst_q[mux_chan][15:8];
297 3'b110: mux_q = hst_q[mux_chan][23:16];
298
299 default: mux_q = 8'd0;
300 endcase
301 end
302
303 control control_unit (
304 .clk(CLK_50MHz),
305 .rx_empty(usb_rx_empty),
306 .tx_full(usb_tx_full),
307 .rx_data(usb_rx_data),
308 .mux_max_byte(mux_max_byte),
309 .mux_min_addr(mux_min_addr),
310 .mux_max_addr(mux_max_addr),
311 .mux_q(mux_q),
312 .mux_reset(mux_reset),
313 .mux_type(mux_type),
314 .mux_chan(mux_chan),
315 .mux_byte(mux_byte),
316 .mux_addr(mux_addr),
317 .rx_rdreq(usb_rx_rdreq),
318 .tx_wrreq(usb_tx_wrreq),
319 .tx_data(usb_tx_data),
320 .led(LED));
321
322endmodule
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