source: trunk/MultiChannelUSB/Paella.v@ 68

Last change on this file since 68 was 68, checked in by demin, 15 years ago

add I2C master and switch from 24 to 32 bit histogram
File size: 7.8 KB
RevLine 
[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
[68]7 inout wire I2C_SDA,
8 output wire I2C_SCL,
9 inout wire [4:0] CON_A,
[27]10 inout wire [15:0] CON_B,
[63]11 input wire [12:0] CON_C,
[27]12 input wire [1:0] CON_BCLK,
13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
[41]17 input wire [2:0] ADC_D,
[27]18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
[30]25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
[27]33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 // Turn output ports off
[65]46/*
[27]47 assign RAM_CLK = 1'b0;
48 assign RAM_CE1 = 1'b0;
49 assign RAM_WE = 1'b0;
50 assign RAM_ADDR = 20'h00000;
[65]51*/
52 assign RAM_CLK = CLK_50MHz;
53 assign RAM_CE1 = 1'b0;
[27]54
55 // Turn inout ports to tri-state
56 assign TRG = 4'bz;
[68]57 assign CON_A = 5'bz;
[27]58 assign CON_B = 16'bz;
[30]59 assign USB_PA0 = 1'bz;
60 assign USB_PA1 = 1'bz;
61 assign USB_PA3 = 1'bz;
62 assign USB_PA7 = 1'bz;
[65]63// assign RAM_DQAP = 1'bz;
64// assign RAM_DQA = 8'bz;
65// assign RAM_DQBP = 1'bz;
66// assign RAM_DQB = 8'bz;
[27]67
[30]68 assign USB_PA2 = ~usb_rden;
69 assign USB_PA4 = usb_addr[0];
70 assign USB_PA5 = usb_addr[1];
71 assign USB_PA6 = ~usb_pktend;
72
[27]73 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[59]74 wire usb_aclr;
75 wire usb_tx_wrreq, usb_rx_rdreq;
76 wire usb_tx_full, usb_rx_empty;
77 wire [7:0] usb_tx_data, usb_rx_data;
[27]78 wire [1:0] usb_addr;
79
80 assign USB_SLRD = ~usb_rdreq;
81 assign USB_SLWR = ~usb_wrreq;
82
[59]83 usb_fifo usb_unit
[27]84 (
85 .usb_clk(USB_IFCLK),
86 .usb_data(USB_PB),
87 .usb_full(~USB_FLAGB),
88 .usb_empty(~USB_FLAGA),
89 .usb_wrreq(usb_wrreq),
90 .usb_rdreq(usb_rdreq),
91 .usb_rden(usb_rden),
92 .usb_pktend(usb_pktend),
93 .usb_addr(usb_addr),
[34]94
[27]95 .clk(CLK_50MHz),
[59]96 .aclr(usb_aclr),
[34]97
[59]98 .tx_full(usb_tx_full),
99 .tx_wrreq(usb_tx_wrreq),
100 .tx_data(usb_tx_data),
[34]101
[59]102 .rx_empty(usb_rx_empty),
103 .rx_rdreq(usb_rx_rdreq),
104 .rx_q(usb_rx_data)
[27]105 );
106
[45]107 reg ana_reset [3:0];
108 wire ana_peak_ready [3:0];
109 wire [11:0] ana_peak [3:0];
[44]110
[45]111 reg osc_reset [3:0];
[59]112 reg [9:0] osc_addr [3:0];
[45]113 wire [9:0] osc_start_addr [3:0];
114 wire [15:0] osc_q [3:0];
[44]115
[45]116 reg hst_reset [3:0];
117 reg [11:0] hst_addr [3:0];
[68]118 wire [31:0] hst_q [3:0];
[27]119
[59]120 wire mux_reset, mux_type;
121 wire [1:0] mux_chan, mux_byte;
122 wire [15:0] mux_addr;
123
[45]124 reg [7:0] mux_q;
[59]125 reg [1:0] mux_max_byte;
126 reg [15:0] mux_min_addr, mux_max_addr;
[44]127
[45]128 wire adc_clk [3:0];
129 wire adc_data_ready [3:0];
130 wire [11:0] adc_data [3:0];
[41]131
[45]132 wire [11:0] raw_data [3:0];
133 wire [11:0] uwt_data [3:0];
134 wire [1:0] uwt_flag [3:0];
135
[63]136 wire [16:0] osc_thrs [3:0];
137 wire adc_pola [3:0];
138
139 assign osc_thrs[0] = 16'd40;
[68]140 assign osc_thrs[1] = 16'd60;
[63]141 assign osc_thrs[2] = 16'd40;
142 assign osc_thrs[3] = 16'd1650;
143
144 assign adc_pola[0] = 1'b1;
145 assign adc_pola[1] = 1'b1;
146 assign adc_pola[2] = 1'b1;
147 assign adc_pola[3] = 1'b0;
148
[45]149 assign adc_clk[0] = ADC_FCO;
150 assign adc_clk[1] = ADC_FCO;
151 assign adc_clk[2] = ADC_FCO;
[63]152
153 assign adc_clk[3] = ADC_FCO;
154/*
155 assign adc_clk[3] = CON_CCLK[0];
156 assign adc_data[3] = CON_C[11:0];
157*/
[68]158/*
[63]159 adc_para adc_para_unit (
160 .lvds_dco(ADC_DCO),
161 .lvds_fco(ADC_FCO),
162 .para_data_ready(CON_CCLK[0]),
163 .para_data(CON_C[11:0]),
164 .adc_data(adc_data[3]));
[68]165*/
[59]166/*
[54]167 wire adc_pll_clk;
168
169 adc_pll adc_pll_unit(
170 .inclk0(ADC_FCO),
171 .c0(adc_pll_clk));
172*/
[59]173/*
174 wire tst_adc_clk;
175 wire [11:0] tst_adc_data;
[48]176
[59]177 test test_unit(
[63]178 .clk(CLK_50MHz),
[59]179 .tst_clk(tst_adc_clk),
180 .tst_data(tst_adc_data));
[48]181
[59]182 assign adc_clk[3] = tst_adc_clk;
183 assign adc_data[3] = tst_adc_data;
184*/
[41]185/*
[38]186 altserial_flash_loader #(
187 .enable_shared_access("OFF"),
188 .enhanced_mode(1),
189 .intended_device_family("Cyclone III")) sfl_unit (
190 .noe(1'b0),
191 .asmi_access_granted(),
192 .asmi_access_request(),
193 .data0out(),
194 .dclkin(),
195 .scein(),
196 .sdoin());
[41]197*/
[54]198
[63]199 adc_lvds #(
200 .size(3),
201 .width(12)) adc_lvds_unit (
[41]202 .lvds_dco(ADC_DCO),
[54]203// .lvds_dco(adc_pll_clk),
[41]204 .lvds_fco(ADC_FCO),
205 .lvds_d(ADC_D),
[68]206 .adc_data({ adc_data[0],
[63]207 adc_data[1],
[68]208 adc_data[2] }));
[44]209
210 genvar i;
211 generate
[68]212 for (i = 0; i < 3; i = i + 1)
[44]213 begin : MCA_CHAIN
214 adc_fifo adc_fifo_unit (
[45]215 .adc_clk(adc_clk[i]),
216 .adc_data(adc_data[i]),
[63]217 .polarity(adc_pola[i]),
[59]218 .clk(CLK_50MHz),
[44]219 .ready(adc_data_ready[i]),
220 .raw_data(raw_data[i]),
221 .uwt_data({uwt_flag[i], uwt_data[i]}));
[27]222
[44]223 analyser analyser_unit (
224 .clk(CLK_50MHz),
225 .reset(ana_reset[i]),
226 .data_ready(adc_data_ready[i]),
227 .uwt_flag(uwt_flag[i]),
228 .uwt_data(uwt_data[i]),
[54]229 .threshold(12'd10),
[44]230 .peak_ready(ana_peak_ready[i]),
231 .peak(ana_peak[i]));
[54]232
[44]233 histogram histogram_unit (
234 .clk(CLK_50MHz),
235 .reset(hst_reset[i]),
236 .data_ready(adc_data_ready[i]),
[63]237 .data(raw_data[i]),
238// .data(uwt_data[i]),
[44]239 .address(hst_addr[i]),
240 .q(hst_q[i]));
[54]241/*
[44]242 histogram histogram_unit (
243 .clk(CLK_50MHz),
244 .reset(hst_reset[i]),
245 .data_ready(ana_peak_ready[i]),
246 .data(ana_peak[i]),
247 .address(hst_addr[i]),
248 .q(hst_q[i]));
[54]249*/
[44]250 oscilloscope oscilloscope_unit (
251 .clk(CLK_50MHz),
252 .reset(osc_reset[i]),
253 .data_ready(adc_data_ready[i]),
254 .raw_data(raw_data[i]),
255 .uwt_data(uwt_data[i]),
[63]256 .threshold(osc_thrs[i]),
[44]257 .address(osc_addr[i]),
258 .start_address(osc_start_addr[i]),
259 .q(osc_q[i]));
260 end
261 endgenerate
[27]262
[46]263 integer j;
264
[44]265 always @*
[27]266 begin
[46]267 for (j = 0; j < 4; j = j + 1)
268 begin
269 osc_reset[j] = 1'b0;
270 osc_addr[j] = 10'b0;
271 hst_reset[j] = 1'b0;
272 hst_addr[j] = 12'b0;
273 end
274
[59]275 case({mux_type, mux_chan})
[45]276 3'b000, 3'b001, 3'b010, 3'b011:
[27]277 begin
[45]278 osc_reset[mux_chan] = mux_reset;
279 osc_addr[mux_chan] = mux_addr[9:0];
280 mux_max_byte = 2'd1;
281 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
[59]282 mux_max_addr = 16'd1023;
[27]283 end
[45]284
285 3'b100, 3'b101, 3'b110, 3'b111:
[27]286 begin
[45]287 hst_reset[mux_chan] = mux_reset;
288 hst_addr[mux_chan] = mux_addr[11:0];
289 mux_max_byte = 2'd2;
290 mux_min_addr = 16'd0;
[68]291 mux_max_addr = 16'd4096;
[27]292 end
293 endcase
294 end
[45]295
296 always @*
297 begin
[59]298 case ({mux_type, mux_byte})
299 3'b000: mux_q = osc_q[mux_chan][7:0];
300 3'b001: mux_q = osc_q[mux_chan][15:8];
[35]301
[59]302 3'b100: mux_q = hst_q[mux_chan][7:0];
303 3'b101: mux_q = hst_q[mux_chan][15:8];
304 3'b110: mux_q = hst_q[mux_chan][23:16];
[68]305 3'b111: mux_q = hst_q[mux_chan][31:24];
[45]306
307 default: mux_q = 8'd0;
308 endcase
309 end
[68]310
311 wire i2c_aclr;
312 wire i2c_wrreq;
313 wire i2c_full;
314 wire [15:0] i2c_data;
315
316 i2c_fifo i2c_unit(
317 .clk(CLK_50MHz),
318 .aclr(i2c_aclr),
319 .wrreq(i2c_wrreq),
320 .data(i2c_data),
321 .full(i2c_full),
322 .i2c_sda(I2C_SDA),
323 .i2c_scl(I2C_SCL));
324
[59]325 control control_unit (
326 .clk(CLK_50MHz),
327 .rx_empty(usb_rx_empty),
328 .tx_full(usb_tx_full),
329 .rx_data(usb_rx_data),
330 .mux_max_byte(mux_max_byte),
331 .mux_min_addr(mux_min_addr),
332 .mux_max_addr(mux_max_addr),
333 .mux_q(mux_q),
334 .mux_reset(mux_reset),
335 .mux_type(mux_type),
336 .mux_chan(mux_chan),
337 .mux_byte(mux_byte),
338 .mux_addr(mux_addr),
339 .rx_rdreq(usb_rx_rdreq),
340 .tx_wrreq(usb_tx_wrreq),
341 .tx_data(usb_tx_data),
[65]342 .ram_we(RAM_WE),
343 .ram_addr(RAM_ADDR),
344 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
[68]345 .i2c_wrreq(i2c_wrreq),
346 .i2c_data(i2c_data),
347 .i2c_full(i2c_full),
[59]348 .led(LED));
[45]349
[54]350endmodule
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