Timeline



Sep 23, 2009:

9:46 PM Changeset [63] by demin
add parameters for number of channels and channel resolution
9:45 PM Changeset [62] by demin
add polarity flag
9:44 PM Changeset [61] by demin
add interface for parallel ADC with unreliable clock
9:42 PM Changeset [60] by demin
interface for parallel ADC with unreliable clock

Sep 18, 2009:

1:40 PM Changeset [59] by demin
move control and test code to separate modules
1:39 PM Changeset [58] by demin
code cleanup

Sep 17, 2009:

6:39 PM Changeset [57] by demin
switch to direct instantiation of altsyncram and dcfifo
6:37 PM Changeset [56] by demin
switch to direct instantiation of altsyncram
6:37 PM Changeset [55] by demin
add pll for lvds interface
6:35 PM Changeset [54] by demin
adapat memory access to normal memory clock
6:32 PM Changeset [53] by demin
add signal invertor
6:31 PM Changeset [52] by demin
switch to normal memory clock

Sep 16, 2009:

12:52 PM Changeset [51] by demin
first attempt to use normal memory clock
12:51 PM Changeset [50] by demin
fix peak detection logic and add peak threshold
12:37 PM Changeset [49] by demin
add registers for output data
12:35 PM Changeset [48] by demin
cleanup test circuit
12:34 PM Changeset [47] by demin
switch to direct instantiation of altsyncram
12:32 PM Changeset [46] by demin
use loop for addr and reset initialisation

Sep 15, 2009:

3:27 AM Changeset [45] by demin
add fourth channel and switch from 32 to 24 bit histogram

Sep 14, 2009:

12:55 AM Changeset [44] by demin
add baseline subtraction

Sep 12, 2009:

12:28 PM Changeset [43] by demin
put back lost PIN_98 and PIN_99
2:04 AM Changeset [42] by demin
code cleanup
1:16 AM Changeset [41] by demin
add one real ADC channel

Sep 11, 2009:

4:21 PM Changeset [40] by demin
turn led off at startup
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