Changeset 41
- Timestamp:
- Sep 12, 2009, 1:16:31 AM (15 years ago)
- Location:
- trunk/MultiChannelUSB
- Files:
-
- 1 added
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/MultiChannelUSB/Paella.dpf
r38 r41 11 11 <pin name="ADC_FCO(n)" direction="Input" source="Assignments" diff_pair_node="ADC_FCO" > 12 12 </pin> 13 <pin name="ADC_D B" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_DB(n)" >13 <pin name="ADC_D[0]" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_D[0](n)" > 14 14 </pin> 15 <pin name="ADC_D B(n)" direction="Input" source="Assignments" diff_pair_node="ADC_DB" >15 <pin name="ADC_D[0](n)" direction="Input" source="Assignments" diff_pair_node="ADC_D[0]" > 16 16 </pin> 17 <pin name="ADC_D C" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_DC(n)" >17 <pin name="ADC_D[1]" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_D[1](n)" > 18 18 </pin> 19 <pin name="ADC_D C(n)" direction="Input" source="Assignments" diff_pair_node="ADC_DC" >19 <pin name="ADC_D[1](n)" direction="Input" source="Assignments" diff_pair_node="ADC_D[1]" > 20 20 </pin> 21 <pin name="ADC_D D" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_DD(n)" >21 <pin name="ADC_D[2]" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_D[2](n)" > 22 22 </pin> 23 <pin name="ADC_D D(n)" direction="Input" source="Assignments" diff_pair_node="ADC_DD" >23 <pin name="ADC_D[2](n)" direction="Input" source="Assignments" diff_pair_node="ADC_D[2]" > 24 24 </pin> 25 25 <pin name="\GEN_ASMI_TYPE_2:asmi_inst~ALTERA_SDO" source="Pin Planner" > -
trunk/MultiChannelUSB/Paella.qsf
r39 r41 48 48 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 49 set_global_assignment -name VERILOG_FILE adc_fifo.v 50 set_global_assignment -name VERILOG_FILE adc_lvds.v 50 51 set_global_assignment -name VERILOG_FILE fifo32x8.v 51 52 set_global_assignment -name VERILOG_FILE fifo32x12.v … … 124 125 set_location_assignment PIN_94 -to "ADC_FCO(n)" 125 126 set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO 126 set_location_assignment PIN_98 -to ADC_DB 127 set_location_assignment PIN_99 -to "ADC_DB(n)" 128 set_instance_assignment -name IO_STANDARD LVDS -to ADC_DB 129 set_location_assignment PIN_108 -to ADC_DC 130 set_location_assignment PIN_109 -to "ADC_DC(n)" 131 set_instance_assignment -name IO_STANDARD LVDS -to ADC_DC 132 set_location_assignment PIN_119 -to ADC_DD 133 set_location_assignment PIN_120 -to "ADC_DD(n)" 134 set_instance_assignment -name IO_STANDARD LVDS -to ADC_DD 127 set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[0] 128 set_location_assignment PIN_108 -to ADC_D[0] 129 set_location_assignment PIN_109 -to "ADC_D[0](n)" 130 set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[1] 131 set_location_assignment PIN_119 -to ADC_D[2] 132 set_location_assignment PIN_120 -to "ADC_D[2](n)" 133 set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[2] 135 134 set_location_assignment PIN_126 -to CON_B[0] 136 135 set_location_assignment PIN_127 -to CON_B[1] -
trunk/MultiChannelUSB/Paella.v
r38 r41 13 13 input wire ADC_DCO, 14 14 input wire ADC_FCO, 15 input wire ADC_DB, 16 input wire ADC_DC, 17 input wire ADC_DD, 15 input wire [2:0] ADC_D, 18 16 19 17 output wire USB_SLRD, … … 133 131 reg adc_data_ready; 134 132 wire adc_clk; 133 135 134 reg [11:0] adc_data; 135 136 wire adc_lvds_clk; 137 wire [11:0] adc_lvds_data [2:0]; 138 136 139 wire [11:0] raw_data; 137 140 wire [11:0] uwt_data; … … 141 144 .inclk0(CLK_50MHz), 142 145 .c0(adc_clk)); 143 146 /* 144 147 altserial_flash_loader #( 145 148 .enable_shared_access("OFF"), … … 153 156 .scein(), 154 157 .sdoin()); 158 */ 159 adc_lvds adc_lvds_unit ( 160 .lvds_dco(ADC_DCO), 161 .lvds_fco(ADC_FCO), 162 .lvds_d(ADC_D), 163 .adc_clk(adc_lvds_clk), 164 .adc_db(adc_lvds_data[0]), 165 .adc_dc(adc_lvds_data[1]), 166 .adc_dd(adc_lvds_data[2])); 155 167 156 168 adc_fifo adc_fifo_unit ( 157 .adc_clk(adc_ clk),158 .adc_data(adc_ data),169 .adc_clk(adc_lvds_clk), 170 .adc_data(adc_lvds_data[1]), 159 171 .aclr(adc_fifo_aclr), 160 172 .rdclk(CLK_50MHz), … … 170 182 .data(raw_data), 171 183 .address(hst_addr), 172 .q(hst_q) 173 ); 184 .q(hst_q)); 174 185 175 186 oscilloscope oscilloscope_unit ( … … 182 193 .address(osc_addr), 183 194 .start_address(osc_start_addr), 184 .q(osc_q) 185 ); 195 .q(osc_q)); 186 196 187 197 /*
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