Changeset 52

Timestamp:

Sep 17, 2009, 6:31:52 PM (16 years ago)

Author:

demin

Message:

switch to normal memory clock

Location:

trunk/MultiChannelUSB

Files:

• histogram.v (modified) (1 diff)
• oscilloscope.v (modified) (4 diffs)

trunk/MultiChannelUSB/histogram.v

@@ -48 +48 @@
                 .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
                 .wren_a(wren_reg),
-                .clock0(~clk),
+                .clock0(clk),
                 .wren_b(1'b0),
                 .address_a(addr_wire),

trunk/MultiChannelUSB/oscilloscope.v

@@ -47 +47 @@
                 .width_byteena_a(1)) osc_ram_unit(
                 .wren_a(wren_reg),
-                .clock0(~clk),
+                .clock0(clk),
                 .address_a(addr_reg),
                 .address_b(address),
@@ -117 +117 @@
                                 addr_next = 10'd0;
                                 data_next = 16'd0;
-                                trig_next = 1'b0;
-                                trig_addr_next = 10'd0;
                                 counter_next = 10'd0;
                         end
@@ -184 +182 @@
                                 addr_next = 10'd0;
                                 data_next = 16'd0;
-                                trig_next = 1'b0;
-                                trig_addr_next = 10'd0;
                                 counter_next = 10'd0;
                         end
@@ -193 +189 @@
         // output logic
         assign  q = q_wire;
-        assign  start_address = trig_reg ? trig_addr_reg ^ 10'h200 : addr_reg + 10'd1;
+        assign  start_address = trig_reg ? (trig_addr_reg ^ 10'h200) + 10'd1: addr_reg + 10'd1;
 
 endmodule