Last change
on this file since 136 was 97, checked in by demin, 14 years ago |
rename several interface wires
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File size:
1.3 KB
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Rev | Line | |
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[27] | 1 | module adc_fifo
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[86] | 2 | #(
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| 3 | parameter W = 48 // fifo width
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| 4 | )
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[27] | 5 | (
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[97] | 6 | input wire adc_clock,
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[86] | 7 | input wire [W-1:0] adc_data,
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[27] | 8 |
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[97] | 9 | input wire sys_clock,
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| 10 | output wire sys_frame,
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[90] | 11 | output wire [W-1:0] sys_data
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[27] | 12 | );
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| 13 |
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[86] | 14 | wire [W-1:0] int_q;
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| 15 | reg [W-1:0] int_data;
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[44] | 16 |
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[97] | 17 | reg state, int_rdreq, int_frame;
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[72] | 18 | wire int_wrfull, int_rdempty;
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[27] | 19 |
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[45] | 20 | dcfifo #(
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| 21 | .intended_device_family("Cyclone III"),
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| 22 | .lpm_numwords(16),
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| 23 | .lpm_showahead("ON"),
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| 24 | .lpm_type("dcfifo"),
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[86] | 25 | .lpm_width(W),
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[45] | 26 | .lpm_widthu(4),
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| 27 | .rdsync_delaypipe(4),
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| 28 | .wrsync_delaypipe(4),
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| 29 | .overflow_checking("ON"),
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| 30 | .underflow_checking("ON"),
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[84] | 31 | .use_eab("ON"),
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[72] | 32 | .write_aclr_synch("OFF")) fifo_unit (
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[58] | 33 | .aclr(1'b0),
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[72] | 34 | .data(adc_data),
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[97] | 35 | .rdclk(sys_clock),
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[49] | 36 | .rdreq((~int_rdempty) & int_rdreq),
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[97] | 37 | .wrclk(adc_clock),
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[72] | 38 | .wrreq(~int_wrfull),
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| 39 | .q(int_q),
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[44] | 40 | .rdempty(int_rdempty),
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[72] | 41 | .wrfull(int_wrfull),
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[45] | 42 | .rdfull(),
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| 43 | .rdusedw(),
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| 44 | .wrempty(),
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| 45 | .wrusedw());
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[27] | 46 |
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[97] | 47 | always @(posedge sys_clock)
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[44] | 48 | begin
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| 49 | case (state)
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[86] | 50 | 1'b0:
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[44] | 51 | begin
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[49] | 52 | int_rdreq <= 1'b1;
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[97] | 53 | int_frame <= 1'b0;
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[86] | 54 | state <= 1'b1;
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[49] | 55 | end
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| 56 |
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[86] | 57 | 1'b1:
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[49] | 58 | begin
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[44] | 59 | if (~int_rdempty)
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| 60 | begin
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[72] | 61 | int_data <= int_q;
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[49] | 62 | int_rdreq <= 1'b0;
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[97] | 63 | int_frame <= 1'b1;
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[86] | 64 | state <= 1'b0;
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[44] | 65 | end
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| 66 | end
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| 67 | endcase
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| 68 | end
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| 69 |
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[97] | 70 | assign sys_frame = int_frame;
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[90] | 71 | assign sys_data = int_data;
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[44] | 72 |
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[27] | 73 | endmodule
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