source: trunk/MultiChannelUSB/Paella.v@ 62

Last change on this file since 62 was 59, checked in by demin, 15 years ago

move control and test code to separate modules
File size: 6.6 KB
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[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
[41]15 input wire [2:0] ADC_D,
[27]16
17 output wire USB_SLRD,
18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 input wire USB_FLAGC,
[30]23 inout wire USB_PA0,
24 inout wire USB_PA1,
25 output wire USB_PA2,
26 inout wire USB_PA3,
27 output wire USB_PA4,
28 output wire USB_PA5,
29 output wire USB_PA6,
30 inout wire USB_PA7,
[27]31 inout wire [7:0] USB_PB,
32
33 output wire RAM_CLK,
34 output wire RAM_CE1,
35 output wire RAM_WE,
36 output wire [19:0] RAM_ADDR,
37 inout wire RAM_DQAP,
38 inout wire [7:0] RAM_DQA,
39 inout wire RAM_DQBP,
40 inout wire [7:0] RAM_DQB
41 );
42
43 // Turn output ports off
44 assign RAM_CLK = 1'b0;
45 assign RAM_CE1 = 1'b0;
46 assign RAM_WE = 1'b0;
47 assign RAM_ADDR = 20'h00000;
48
49 // Turn inout ports to tri-state
50 assign TRG = 4'bz;
51 assign CON_A = 7'bz;
52 assign CON_B = 16'bz;
53 assign CON_C = 13'bz;
[30]54 assign USB_PA0 = 1'bz;
55 assign USB_PA1 = 1'bz;
56 assign USB_PA3 = 1'bz;
57 assign USB_PA7 = 1'bz;
[27]58 assign RAM_DQAP = 1'bz;
59 assign RAM_DQA = 8'bz;
60 assign RAM_DQBP = 1'bz;
61 assign RAM_DQB = 8'bz;
62
[30]63 assign USB_PA2 = ~usb_rden;
64 assign USB_PA4 = usb_addr[0];
65 assign USB_PA5 = usb_addr[1];
66 assign USB_PA6 = ~usb_pktend;
67
[27]68 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[59]69 wire usb_aclr;
70 wire usb_tx_wrreq, usb_rx_rdreq;
71 wire usb_tx_full, usb_rx_empty;
72 wire [7:0] usb_tx_data, usb_rx_data;
[27]73 wire [1:0] usb_addr;
74
75 assign USB_SLRD = ~usb_rdreq;
76 assign USB_SLWR = ~usb_wrreq;
77
[59]78 usb_fifo usb_unit
[27]79 (
80 .usb_clk(USB_IFCLK),
81 .usb_data(USB_PB),
82 .usb_full(~USB_FLAGB),
83 .usb_empty(~USB_FLAGA),
84 .usb_wrreq(usb_wrreq),
85 .usb_rdreq(usb_rdreq),
86 .usb_rden(usb_rden),
87 .usb_pktend(usb_pktend),
88 .usb_addr(usb_addr),
[34]89
[27]90 .clk(CLK_50MHz),
[59]91 .aclr(usb_aclr),
[34]92
[59]93 .tx_full(usb_tx_full),
94 .tx_wrreq(usb_tx_wrreq),
95 .tx_data(usb_tx_data),
[34]96
[59]97 .rx_empty(usb_rx_empty),
98 .rx_rdreq(usb_rx_rdreq),
99 .rx_q(usb_rx_data)
[27]100 );
101
[45]102 reg ana_reset [3:0];
103 wire ana_peak_ready [3:0];
104 wire [11:0] ana_peak [3:0];
[44]105
[45]106 reg osc_reset [3:0];
[59]107 reg [9:0] osc_addr [3:0];
[45]108 wire [9:0] osc_start_addr [3:0];
109 wire [15:0] osc_q [3:0];
[44]110
[45]111 reg hst_reset [3:0];
112 reg [11:0] hst_addr [3:0];
113 wire [23:0] hst_q [3:0];
[27]114
[59]115 wire mux_reset, mux_type;
116 wire [1:0] mux_chan, mux_byte;
117 wire [15:0] mux_addr;
118
[45]119 reg [7:0] mux_q;
[59]120 reg [1:0] mux_max_byte;
121 reg [15:0] mux_min_addr, mux_max_addr;
[44]122
[45]123 wire adc_clk [3:0];
124 wire adc_data_ready [3:0];
125 wire [11:0] adc_data [3:0];
[41]126
[45]127 wire [11:0] raw_data [3:0];
128 wire [11:0] uwt_data [3:0];
129 wire [1:0] uwt_flag [3:0];
130
131 assign adc_clk[0] = ADC_FCO;
132 assign adc_clk[1] = ADC_FCO;
133 assign adc_clk[2] = ADC_FCO;
[54]134
[45]135 assign adc_clk[3] = CON_B[0];
136 assign adc_data[3] = CON_B[12:1];
[59]137/*
[54]138 wire adc_pll_clk;
139
140 adc_pll adc_pll_unit(
141 .inclk0(ADC_FCO),
142 .c0(adc_pll_clk));
143*/
[59]144/*
145 wire tst_adc_clk;
146 wire [11:0] tst_adc_data;
[48]147
[59]148 test test_unit(
[27]149 .inclk0(CLK_50MHz),
[59]150 .tst_clk(tst_adc_clk),
151 .tst_data(tst_adc_data));
[48]152
[59]153 assign adc_clk[3] = tst_adc_clk;
154 assign adc_data[3] = tst_adc_data;
155*/
[41]156/*
[38]157 altserial_flash_loader #(
158 .enable_shared_access("OFF"),
159 .enhanced_mode(1),
160 .intended_device_family("Cyclone III")) sfl_unit (
161 .noe(1'b0),
162 .asmi_access_granted(),
163 .asmi_access_request(),
164 .data0out(),
165 .dclkin(),
166 .scein(),
167 .sdoin());
[41]168*/
[54]169
[41]170 adc_lvds adc_lvds_unit (
171 .lvds_dco(ADC_DCO),
[54]172// .lvds_dco(adc_pll_clk),
[41]173 .lvds_fco(ADC_FCO),
174 .lvds_d(ADC_D),
[59]175 .adc_db(adc_data[2]),
[45]176 .adc_dc(adc_data[1]),
[59]177 .adc_dd(adc_data[0]));
[44]178
179 genvar i;
180 generate
[59]181 for (i = 2; i < 4; i = i + 1)
[44]182 begin : MCA_CHAIN
183 adc_fifo adc_fifo_unit (
[45]184 .adc_clk(adc_clk[i]),
185 .adc_data(adc_data[i]),
[59]186 .clk(CLK_50MHz),
[44]187 .ready(adc_data_ready[i]),
188 .raw_data(raw_data[i]),
189 .uwt_data({uwt_flag[i], uwt_data[i]}));
[27]190
[44]191 analyser analyser_unit (
192 .clk(CLK_50MHz),
193 .reset(ana_reset[i]),
194 .data_ready(adc_data_ready[i]),
195 .uwt_flag(uwt_flag[i]),
196 .uwt_data(uwt_data[i]),
[54]197 .threshold(12'd10),
[44]198 .peak_ready(ana_peak_ready[i]),
199 .peak(ana_peak[i]));
[54]200
[44]201 histogram histogram_unit (
202 .clk(CLK_50MHz),
203 .reset(hst_reset[i]),
204 .data_ready(adc_data_ready[i]),
[54]205// .data(raw_data[i]),
206 .data(uwt_data[i]),
[44]207 .address(hst_addr[i]),
208 .q(hst_q[i]));
[54]209/*
[44]210 histogram histogram_unit (
211 .clk(CLK_50MHz),
212 .reset(hst_reset[i]),
213 .data_ready(ana_peak_ready[i]),
214 .data(ana_peak[i]),
215 .address(hst_addr[i]),
216 .q(hst_q[i]));
[54]217*/
[44]218 oscilloscope oscilloscope_unit (
219 .clk(CLK_50MHz),
220 .reset(osc_reset[i]),
221 .data_ready(adc_data_ready[i]),
222 .raw_data(raw_data[i]),
223 .uwt_data(uwt_data[i]),
[54]224 .threshold(16'd40),
[44]225 .address(osc_addr[i]),
226 .start_address(osc_start_addr[i]),
227 .q(osc_q[i]));
228 end
229 endgenerate
[27]230
[46]231 integer j;
232
[44]233 always @*
[27]234 begin
[46]235 for (j = 0; j < 4; j = j + 1)
236 begin
237 osc_reset[j] = 1'b0;
238 osc_addr[j] = 10'b0;
239 hst_reset[j] = 1'b0;
240 hst_addr[j] = 12'b0;
241 end
242
[59]243 case({mux_type, mux_chan})
[45]244 3'b000, 3'b001, 3'b010, 3'b011:
[27]245 begin
[45]246 osc_reset[mux_chan] = mux_reset;
247 osc_addr[mux_chan] = mux_addr[9:0];
248 mux_max_byte = 2'd1;
249 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
[59]250 mux_max_addr = 16'd1023;
[27]251 end
[45]252
253 3'b100, 3'b101, 3'b110, 3'b111:
[27]254 begin
[45]255 hst_reset[mux_chan] = mux_reset;
256 hst_addr[mux_chan] = mux_addr[11:0];
257 mux_max_byte = 2'd2;
258 mux_min_addr = 16'd0;
[59]259 mux_max_addr = 16'd4095;
[27]260 end
261 endcase
262 end
[45]263
264 always @*
265 begin
[59]266 case ({mux_type, mux_byte})
267 3'b000: mux_q = osc_q[mux_chan][7:0];
268 3'b001: mux_q = osc_q[mux_chan][15:8];
[35]269
[59]270 3'b100: mux_q = hst_q[mux_chan][7:0];
271 3'b101: mux_q = hst_q[mux_chan][15:8];
272 3'b110: mux_q = hst_q[mux_chan][23:16];
[45]273
274 default: mux_q = 8'd0;
275 endcase
276 end
277
[59]278 control control_unit (
279 .clk(CLK_50MHz),
280 .rx_empty(usb_rx_empty),
281 .tx_full(usb_tx_full),
282 .rx_data(usb_rx_data),
283 .mux_max_byte(mux_max_byte),
284 .mux_min_addr(mux_min_addr),
285 .mux_max_addr(mux_max_addr),
286 .mux_q(mux_q),
287 .mux_reset(mux_reset),
288 .mux_type(mux_type),
289 .mux_chan(mux_chan),
290 .mux_byte(mux_byte),
291 .mux_addr(mux_addr),
292 .rx_rdreq(usb_rx_rdreq),
293 .tx_wrreq(usb_tx_wrreq),
294 .tx_data(usb_tx_data),
295 .led(LED));
[45]296
[54]297endmodule
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