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source: trunk/MultiChannelUSB/Paella.v@ 55

Last change on this file since 55 was 54, checked in by demin, 15 years ago
adapat memory access to normal memory clock
File size: 9.7 KB

Rev	Line
[27]	1	module Paella
	2	(
	3	input wire CLK_50MHz,
	4	output wire LED,
	5
	6	inout wire [3:0] TRG,
	7	inout wire [6:0] CON_A,
	8	inout wire [15:0] CON_B,
	9	inout wire [12:0] CON_C,
	10	input wire [1:0] CON_BCLK,
	11	input wire [1:0] CON_CCLK,
	12
	13	input wire ADC_DCO,
	14	input wire ADC_FCO,
[41]	15	input wire [2:0] ADC_D,
[27]	16
	17	output wire USB_SLRD,
	18	output wire USB_SLWR,
	19	input wire USB_IFCLK,
	20	input wire USB_FLAGA, // EMPTY flag for EP6
	21	input wire USB_FLAGB, // FULL flag for EP8
	22	input wire USB_FLAGC,
[30]	23	inout wire USB_PA0,
	24	inout wire USB_PA1,
	25	output wire USB_PA2,
	26	inout wire USB_PA3,
	27	output wire USB_PA4,
	28	output wire USB_PA5,
	29	output wire USB_PA6,
	30	inout wire USB_PA7,
[27]	31	inout wire [7:0] USB_PB,
	32
	33	output wire RAM_CLK,
	34	output wire RAM_CE1,
	35	output wire RAM_WE,
	36	output wire [19:0] RAM_ADDR,
	37	inout wire RAM_DQAP,
	38	inout wire [7:0] RAM_DQA,
	39	inout wire RAM_DQBP,
	40	inout wire [7:0] RAM_DQB
	41	);
	42
	43	// Turn output ports off
	44	assign RAM_CLK = 1'b0;
	45	assign RAM_CE1 = 1'b0;
	46	assign RAM_WE = 1'b0;
	47	assign RAM_ADDR = 20'h00000;
	48
	49	// Turn inout ports to tri-state
	50	assign TRG = 4'bz;
	51	assign CON_A = 7'bz;
	52	assign CON_B = 16'bz;
	53	assign CON_C = 13'bz;
[30]	54	assign USB_PA0 = 1'bz;
	55	assign USB_PA1 = 1'bz;
	56	assign USB_PA3 = 1'bz;
	57	assign USB_PA7 = 1'bz;
[27]	58	assign RAM_DQAP = 1'bz;
	59	assign RAM_DQA = 8'bz;
	60	assign RAM_DQBP = 1'bz;
	61	assign RAM_DQB = 8'bz;
	62
[30]	63	assign USB_PA2 = ~usb_rden;
	64	assign USB_PA4 = usb_addr[0];
	65	assign USB_PA5 = usb_addr[1];
	66	assign USB_PA6 = ~usb_pktend;
	67
[31]	68	reg led_reg;
	69	assign LED = led_reg;
[27]	70
	71	wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[35]	72	wire usb_fifo_aclr;
[30]	73	reg usb_fifo_tx_wrreq;
	74	reg usb_fifo_rx_rdreq;
[27]	75	wire usb_fifo_tx_full, usb_fifo_rx_empty;
[30]	76	reg [7:0] usb_fifo_tx_data;
	77	wire [7:0] usb_fifo_rx_data;
[27]	78	wire [1:0] usb_addr;
	79
	80	assign USB_SLRD = ~usb_rdreq;
	81	assign USB_SLWR = ~usb_wrreq;
	82
	83	usb_fifo usb_fifo_unit
	84	(
	85	.usb_clk(USB_IFCLK),
	86	.usb_data(USB_PB),
	87	.usb_full(~USB_FLAGB),
	88	.usb_empty(~USB_FLAGA),
	89	.usb_wrreq(usb_wrreq),
	90	.usb_rdreq(usb_rdreq),
	91	.usb_rden(usb_rden),
	92	.usb_pktend(usb_pktend),
	93	.usb_addr(usb_addr),
[34]	94
[27]	95	.clk(CLK_50MHz),
	96	.aclr(usb_fifo_aclr),
[34]	97
	98	.tx_full(usb_fifo_tx_full),
	99	.tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
[27]	100	.tx_data(usb_fifo_tx_data),
[34]	101
[27]	102	.rx_empty(usb_fifo_rx_empty),
[37]	103	.rx_rdreq((~usb_fifo_rx_empty) & usb_fifo_rx_rdreq),
[35]	104	.rx_q(usb_fifo_rx_data)
[27]	105	);
	106
[37]	107	reg [23:0] rx_counter;
[35]	108	reg [10:0] tst_counter;
	109
[45]	110	reg ana_reset [3:0];
	111	wire ana_peak_ready [3:0];
	112	wire [11:0] ana_peak [3:0];
[44]	113
[45]	114	reg osc_reset [3:0];
	115	wire [9:0] osc_start_addr [3:0];
	116	reg [9:0] osc_addr [3:0];
	117	wire [15:0] osc_q [3:0];
[44]	118	reg [15:0] osc_q_mux;
	119
[45]	120	reg hst_reset [3:0];
	121	reg [11:0] hst_addr [3:0];
	122	wire [23:0] hst_q [3:0];
[27]	123
[45]	124	reg mux_reset, mux_type;
	125	reg [1:0] mux_chan, mux_byte, mux_max_byte;
[48]	126	reg [15:0] mux_addr, mux_min_addr, mux_max_addr, mux_num_addr;
[45]	127	reg [7:0] mux_q;
[44]	128
[45]	129	reg [3:0] state1, state2;
[27]	130	reg adc_fifo_aclr;
	131
[45]	132	wire adc_clk [3:0];
[41]	133
	134
[45]	135	wire adc_data_ready [3:0];
	136	wire [11:0] adc_data [3:0];
[41]	137
[45]	138	wire [11:0] raw_data [3:0];
	139	wire [11:0] uwt_data [3:0];
	140	wire [1:0] uwt_flag [3:0];
	141
	142	assign adc_clk[0] = ADC_FCO;
	143	assign adc_clk[1] = ADC_FCO;
	144	assign adc_clk[2] = ADC_FCO;
[54]	145
[45]	146	assign adc_clk[3] = CON_B[0];
	147	assign adc_data[3] = CON_B[12:1];
[54]	148
	149	wire adc_pll_clk;
	150
[48]	151	wire tst_adc_clk;
	152	reg [11:0] tst_adc_data;
[54]	153	/*
[48]	154	assign adc_clk[3] = tst_adc_clk;
	155	assign adc_data[3] = tst_adc_data;
[54]	156	*/
	157	/*
	158	adc_pll adc_pll_unit(
	159	.inclk0(ADC_FCO),
	160	.c0(adc_pll_clk));
	161	*/
[48]	162
[27]	163	pll pll_unit(
	164	.inclk0(CLK_50MHz),
[48]	165	.c0(tst_adc_clk));
	166
[41]	167	/*
[38]	168	altserial_flash_loader #(
	169	.enable_shared_access("OFF"),
	170	.enhanced_mode(1),
	171	.intended_device_family("Cyclone III")) sfl_unit (
	172	.noe(1'b0),
	173	.asmi_access_granted(),
	174	.asmi_access_request(),
	175	.data0out(),
	176	.dclkin(),
	177	.scein(),
	178	.sdoin());
[41]	179	*/
[54]	180
[41]	181	adc_lvds adc_lvds_unit (
	182	.lvds_dco(ADC_DCO),
[54]	183	// .lvds_dco(adc_pll_clk),
[41]	184	.lvds_fco(ADC_FCO),
	185	.lvds_d(ADC_D),
[45]	186	.adc_db(adc_data[0]),
	187	.adc_dc(adc_data[1]),
	188	.adc_dd(adc_data[2]));
[44]	189
	190	genvar i;
	191	generate
[54]	192	for (i = 0; i < 4; i = i + 1)
[44]	193	begin : MCA_CHAIN
	194	adc_fifo adc_fifo_unit (
[45]	195	.adc_clk(adc_clk[i]),
	196	.adc_data(adc_data[i]),
[44]	197	.aclr(adc_fifo_aclr),
	198	.rdclk(CLK_50MHz),
	199	.ready(adc_data_ready[i]),
	200	.raw_data(raw_data[i]),
	201	.uwt_data({uwt_flag[i], uwt_data[i]}));
[27]	202
[44]	203	analyser analyser_unit (
	204	.clk(CLK_50MHz),
	205	.reset(ana_reset[i]),
	206	.data_ready(adc_data_ready[i]),
	207	.uwt_flag(uwt_flag[i]),
	208	.uwt_data(uwt_data[i]),
[54]	209	.threshold(12'd10),
[44]	210	.peak_ready(ana_peak_ready[i]),
	211	.peak(ana_peak[i]));
[54]	212
[44]	213	histogram histogram_unit (
	214	.clk(CLK_50MHz),
	215	.reset(hst_reset[i]),
	216	.data_ready(adc_data_ready[i]),
[54]	217	// .data(raw_data[i]),
	218	.data(uwt_data[i]),
[44]	219	.address(hst_addr[i]),
	220	.q(hst_q[i]));
[54]	221	/*
[44]	222	histogram histogram_unit (
	223	.clk(CLK_50MHz),
	224	.reset(hst_reset[i]),
	225	.data_ready(ana_peak_ready[i]),
	226	.data(ana_peak[i]),
	227	.address(hst_addr[i]),
	228	.q(hst_q[i]));
[54]	229	*/
[44]	230	oscilloscope oscilloscope_unit (
	231	.clk(CLK_50MHz),
	232	.reset(osc_reset[i]),
	233	.data_ready(adc_data_ready[i]),
	234	.raw_data(raw_data[i]),
	235	.uwt_data(uwt_data[i]),
[54]	236	.threshold(16'd40),
[44]	237	.address(osc_addr[i]),
	238	.start_address(osc_start_addr[i]),
	239	.q(osc_q[i]));
	240	end
	241	endgenerate
[27]	242
[46]	243	integer j;
	244
[44]	245	always @*
[27]	246	begin
[46]	247	for (j = 0; j < 4; j = j + 1)
	248	begin
	249	osc_reset[j] = 1'b0;
	250	osc_addr[j] = 10'b0;
	251	hst_reset[j] = 1'b0;
	252	hst_addr[j] = 12'b0;
	253	end
	254
[45]	255	case({mux_type,mux_chan})
	256	3'b000, 3'b001, 3'b010, 3'b011:
[27]	257	begin
[45]	258	osc_reset[mux_chan] = mux_reset;
	259	osc_addr[mux_chan] = mux_addr[9:0];
	260	mux_max_byte = 2'd1;
	261	mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
[48]	262	mux_num_addr = 16'd1023;
[27]	263	end
[45]	264
	265	3'b100, 3'b101, 3'b110, 3'b111:
[27]	266	begin
[45]	267	hst_reset[mux_chan] = mux_reset;
	268	hst_addr[mux_chan] = mux_addr[11:0];
	269	mux_max_byte = 2'd2;
	270	mux_min_addr = 16'd0;
[48]	271	mux_num_addr = 16'd4095;
[27]	272	end
	273	endcase
	274	end
[45]	275
	276	always @*
	277	begin
	278	case ({mux_type,mux_byte})
	279	5'b000: mux_q = osc_q[mux_chan][7:0];
	280	5'b001: mux_q = osc_q[mux_chan][15:8];
[35]	281
[45]	282	5'b100: mux_q = hst_q[mux_chan][7:0];
	283	5'b101: mux_q = hst_q[mux_chan][15:8];
	284	5'b110: mux_q = hst_q[mux_chan][23:16];
	285
	286	default: mux_q = 8'd0;
	287	endcase
	288	end
	289
	290
[30]	291	always @(posedge CLK_50MHz)
	292	begin
[37]	293	if (~usb_fifo_rx_empty)
	294	begin
	295	led_reg <= 1'b0;
	296	rx_counter <= 24'd0;
	297	end
	298	else
	299	begin
	300	if (&rx_counter)
	301	begin
	302	led_reg <= 1'b1;
	303	end
	304	else
	305	begin
	306	rx_counter <= rx_counter + 24'd1;
	307	end
	308	end
	309
[35]	310	case(state1)
[30]	311	1:
	312	begin
[37]	313	usb_fifo_rx_rdreq <= 1'b1;
[30]	314	usb_fifo_tx_wrreq <= 1'b0;
[45]	315	mux_type <= 1'b0;
	316	mux_chan <= 2'd0;
	317	mux_byte <= 2'd0;
	318	mux_reset <= 1'b0;
[35]	319	state1 <= 4'd2;
[30]	320	end
	321
	322	2:
	323	begin
	324	if (~usb_fifo_rx_empty)
	325	begin
	326	case (usb_fifo_rx_data)
[45]	327	8'h40, 8'h41, 8'h42, 8'h43, 8'h50, 8'h51, 8'h52, 8'h53:
[30]	328	begin
[37]	329	usb_fifo_rx_rdreq <= 1'b0;
[45]	330	mux_type <= usb_fifo_rx_data[4];
	331	mux_chan <= usb_fifo_rx_data[1:0];
	332	mux_reset <= 1'b1;
[35]	333	state1 <= 4'd1;
[30]	334	end
[45]	335
	336	8'h60, 8'h61, 8'h62, 8'h63, 8'h70, 8'h71, 8'h72, 8'h73:
[30]	337	begin
[37]	338	usb_fifo_rx_rdreq <= 1'b0;
[45]	339	mux_type <= usb_fifo_rx_data[4];
	340	mux_chan <= usb_fifo_rx_data[1:0];
[35]	341	state1 <= 4'd3;
[30]	342	end
[45]	343
[44]	344	8'h30:
[35]	345	begin
[37]	346	usb_fifo_rx_rdreq <= 1'b0;
[35]	347	state1 <= 4'd1;
	348	end
[45]	349
[44]	350	8'h31:
[35]	351	begin
[37]	352	usb_fifo_rx_rdreq <= 1'b0;
[35]	353	tst_counter <= 11'd0;
[54]	354	state1 <= 4'd6;
[35]	355	end
[30]	356	endcase
	357	end
	358	end
[45]	359	// mux transfer
[30]	360	3:
	361	begin
[45]	362	mux_addr <= mux_min_addr;
[48]	363	mux_max_addr <= mux_min_addr + mux_num_addr;
[45]	364	mux_byte <= 2'd0;
[35]	365	state1 <= 4'd4;
	366	end
[54]	367
[35]	368	4:
	369	begin
[54]	370	usb_fifo_tx_wrreq <= 1'b0;
[45]	371	state1 <= 4'd5;
[30]	372	end
[54]	373
[34]	374	5:
	375	begin
	376	if (~usb_fifo_tx_full)
	377	begin
[45]	378	usb_fifo_tx_data <= mux_q;
[54]	379	usb_fifo_tx_wrreq <= 1'b1;
[45]	380	if ((mux_byte == mux_max_byte) && (mux_addr == mux_max_addr))
[30]	381	begin
[54]	382	state1 <= 4'd1;
[30]	383	end
[35]	384	else
[34]	385	begin
[54]	386	state1 <= 4'd4;
[45]	387	if (mux_byte == mux_max_byte)
[35]	388	begin
[45]	389	mux_addr <= mux_addr + 16'd1;
	390	mux_byte <= 2'd0;
[35]	391	end
[45]	392	else
	393	begin
	394	mux_byte <= mux_byte + 2'd1;
	395	end
[34]	396	end
[30]	397	end
	398	end
[54]	399
	400	// tst transfer
[45]	401	6:
[30]	402	begin
[35]	403	usb_fifo_tx_data <= tst_counter;
[34]	404	usb_fifo_tx_wrreq <= 1'b1;
[35]	405	tst_counter <= tst_counter + 11'd1;
[45]	406	state1 <= 4'd8;
[34]	407	end
[54]	408	7:
[34]	409	begin
	410	if (~usb_fifo_tx_full)
[30]	411	begin
[35]	412	usb_fifo_tx_data <= tst_counter;
[48]	413	if (tst_counter == 11'd0)
[34]	414	begin
[45]	415	state1 <= 4'd9;
[34]	416	end
	417	else
	418	begin
[35]	419	tst_counter <= tst_counter + 11'd1;
[34]	420	end
[30]	421	end
	422	end
[54]	423	8:
[30]	424	begin
[34]	425	if (~usb_fifo_tx_full)
[30]	426	begin
[34]	427	usb_fifo_tx_wrreq <= 1'b0;
[35]	428	state1 <= 4'd1;
[30]	429	end
	430	end
[35]	431
	432	default:
	433	begin
	434	state1 <= 4'd1;
	435	end
[30]	436	endcase
	437	end
[48]	438
	439	always @ (posedge tst_adc_clk)
[27]	440	begin
	441	case (state2)
	442	1:
	443	begin
[48]	444	tst_adc_data <= 12'd0;
[35]	445	state2 <= 4'd2;
[27]	446	end
	447
	448	2:
	449	begin
[48]	450	tst_adc_data <= 12'd1024;
[35]	451	state2 <= 4'd3;
[27]	452	end
	453
	454	3:
	455	begin
[48]	456	tst_adc_data <= 12'd2048;
[35]	457	state2 <= 4'd4;
[27]	458	end
	459
	460	4:
	461	begin
[48]	462	tst_adc_data <= 12'd3072;
[35]	463	state2 <= 4'd5;
[27]	464	end
	465
	466	5:
	467	begin
[48]	468	tst_adc_data <= 12'd4095;
[35]	469	state2 <= 4'd1;
[27]	470	end
	471
	472	default:
	473	begin
[35]	474	state2 <= 4'd1;
[27]	475	end
	476	endcase
	477	end
[48]	478
[54]	479	endmodule

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