source: trunk/MultiChannelUSB/Paella.v@ 50

Last change on this file since 50 was 50, checked in by demin, 15 years ago

fix peak detection logic and add peak threshold
File size: 9.6 KB
RevLine 
[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
[41]15 input wire [2:0] ADC_D,
[27]16
17 output wire USB_SLRD,
18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 input wire USB_FLAGC,
[30]23 inout wire USB_PA0,
24 inout wire USB_PA1,
25 output wire USB_PA2,
26 inout wire USB_PA3,
27 output wire USB_PA4,
28 output wire USB_PA5,
29 output wire USB_PA6,
30 inout wire USB_PA7,
[27]31 inout wire [7:0] USB_PB,
32
33 output wire RAM_CLK,
34 output wire RAM_CE1,
35 output wire RAM_WE,
36 output wire [19:0] RAM_ADDR,
37 inout wire RAM_DQAP,
38 inout wire [7:0] RAM_DQA,
39 inout wire RAM_DQBP,
40 inout wire [7:0] RAM_DQB
41 );
42
43 // Turn output ports off
44 assign RAM_CLK = 1'b0;
45 assign RAM_CE1 = 1'b0;
46 assign RAM_WE = 1'b0;
47 assign RAM_ADDR = 20'h00000;
48
49 // Turn inout ports to tri-state
50 assign TRG = 4'bz;
51 assign CON_A = 7'bz;
52 assign CON_B = 16'bz;
53 assign CON_C = 13'bz;
[30]54 assign USB_PA0 = 1'bz;
55 assign USB_PA1 = 1'bz;
56 assign USB_PA3 = 1'bz;
57 assign USB_PA7 = 1'bz;
[27]58 assign RAM_DQAP = 1'bz;
59 assign RAM_DQA = 8'bz;
60 assign RAM_DQBP = 1'bz;
61 assign RAM_DQB = 8'bz;
62
[30]63 assign USB_PA2 = ~usb_rden;
64 assign USB_PA4 = usb_addr[0];
65 assign USB_PA5 = usb_addr[1];
66 assign USB_PA6 = ~usb_pktend;
67
[31]68 reg led_reg;
69 assign LED = led_reg;
[27]70
71 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[35]72 wire usb_fifo_aclr;
[30]73 reg usb_fifo_tx_wrreq;
74 reg usb_fifo_rx_rdreq;
[27]75 wire usb_fifo_tx_full, usb_fifo_rx_empty;
[30]76 reg [7:0] usb_fifo_tx_data;
77 wire [7:0] usb_fifo_rx_data;
[27]78 wire [1:0] usb_addr;
79
80 assign USB_SLRD = ~usb_rdreq;
81 assign USB_SLWR = ~usb_wrreq;
82
83 usb_fifo usb_fifo_unit
84 (
85 .usb_clk(USB_IFCLK),
86 .usb_data(USB_PB),
87 .usb_full(~USB_FLAGB),
88 .usb_empty(~USB_FLAGA),
89 .usb_wrreq(usb_wrreq),
90 .usb_rdreq(usb_rdreq),
91 .usb_rden(usb_rden),
92 .usb_pktend(usb_pktend),
93 .usb_addr(usb_addr),
[34]94
[27]95 .clk(CLK_50MHz),
96 .aclr(usb_fifo_aclr),
[34]97
98 .tx_full(usb_fifo_tx_full),
99 .tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
[27]100 .tx_data(usb_fifo_tx_data),
[34]101
[27]102 .rx_empty(usb_fifo_rx_empty),
[37]103 .rx_rdreq((~usb_fifo_rx_empty) & usb_fifo_rx_rdreq),
[35]104 .rx_q(usb_fifo_rx_data)
[27]105 );
106
[37]107 reg [23:0] rx_counter;
[35]108 reg [10:0] tst_counter;
109
[45]110 reg ana_reset [3:0];
111 wire ana_peak_ready [3:0];
112 wire [11:0] ana_peak [3:0];
[44]113
[45]114 reg osc_reset [3:0];
115 wire [9:0] osc_start_addr [3:0];
116 reg [9:0] osc_addr [3:0];
117 wire [15:0] osc_q [3:0];
[44]118 reg [15:0] osc_q_mux;
119
[45]120 reg hst_reset [3:0];
121 reg [11:0] hst_addr [3:0];
122 wire [23:0] hst_q [3:0];
[27]123
[45]124 reg mux_reset, mux_type;
125 reg [1:0] mux_chan, mux_byte, mux_max_byte;
[48]126 reg [15:0] mux_addr, mux_min_addr, mux_max_addr, mux_num_addr;
[45]127 reg [7:0] mux_q;
[44]128
[45]129 reg [3:0] state1, state2;
[27]130 reg adc_fifo_aclr;
131
[45]132 wire adc_clk [3:0];
[41]133
134
[45]135 wire adc_data_ready [3:0];
136 wire [11:0] adc_data [3:0];
[41]137
[45]138 wire [11:0] raw_data [3:0];
139 wire [11:0] uwt_data [3:0];
140 wire [1:0] uwt_flag [3:0];
141
142 assign adc_clk[0] = ADC_FCO;
143 assign adc_clk[1] = ADC_FCO;
144 assign adc_clk[2] = ADC_FCO;
[48]145/*
[45]146 assign adc_clk[3] = CON_B[0];
147 assign adc_data[3] = CON_B[12:1];
[48]148*/
149 wire tst_adc_clk;
150 reg [11:0] tst_adc_data;
151
152 assign adc_clk[3] = tst_adc_clk;
153 assign adc_data[3] = tst_adc_data;
154
[27]155 pll pll_unit(
156 .inclk0(CLK_50MHz),
[48]157 .c0(tst_adc_clk));
158
[41]159/*
[38]160 altserial_flash_loader #(
161 .enable_shared_access("OFF"),
162 .enhanced_mode(1),
163 .intended_device_family("Cyclone III")) sfl_unit (
164 .noe(1'b0),
165 .asmi_access_granted(),
166 .asmi_access_request(),
167 .data0out(),
168 .dclkin(),
169 .scein(),
170 .sdoin());
[41]171*/
172 adc_lvds adc_lvds_unit (
173 .lvds_dco(ADC_DCO),
174 .lvds_fco(ADC_FCO),
175 .lvds_d(ADC_D),
[45]176 .adc_db(adc_data[0]),
177 .adc_dc(adc_data[1]),
178 .adc_dd(adc_data[2]));
[44]179
180 genvar i;
181 generate
[48]182 for (i = 2; i < 4; i = i + 1)
[44]183 begin : MCA_CHAIN
184 adc_fifo adc_fifo_unit (
[45]185 .adc_clk(adc_clk[i]),
186 .adc_data(adc_data[i]),
[44]187 .aclr(adc_fifo_aclr),
188 .rdclk(CLK_50MHz),
189 .ready(adc_data_ready[i]),
190 .raw_data(raw_data[i]),
191 .uwt_data({uwt_flag[i], uwt_data[i]}));
[27]192
[44]193 analyser analyser_unit (
194 .clk(CLK_50MHz),
195 .reset(ana_reset[i]),
196 .data_ready(adc_data_ready[i]),
197 .uwt_flag(uwt_flag[i]),
198 .uwt_data(uwt_data[i]),
[50]199 .threshold(12'd5),
[44]200 .peak_ready(ana_peak_ready[i]),
201 .peak(ana_peak[i]));
202/*
203 histogram histogram_unit (
204 .clk(CLK_50MHz),
205 .reset(hst_reset[i]),
206 .data_ready(adc_data_ready[i]),
207 .data(raw_data[i]),
208 .address(hst_addr[i]),
209 .q(hst_q[i]));
210*/
211 histogram histogram_unit (
212 .clk(CLK_50MHz),
213 .reset(hst_reset[i]),
214 .data_ready(ana_peak_ready[i]),
215 .data(ana_peak[i]),
216 .address(hst_addr[i]),
217 .q(hst_q[i]));
218
219 oscilloscope oscilloscope_unit (
220 .clk(CLK_50MHz),
221 .reset(osc_reset[i]),
222 .data_ready(adc_data_ready[i]),
223 .raw_data(raw_data[i]),
224 .uwt_data(uwt_data[i]),
225 .threshold(16'd100),
226 .address(osc_addr[i]),
227 .start_address(osc_start_addr[i]),
228 .q(osc_q[i]));
229 end
230 endgenerate
[27]231
[46]232 integer j;
233
[44]234 always @*
[27]235 begin
[46]236 for (j = 0; j < 4; j = j + 1)
237 begin
238 osc_reset[j] = 1'b0;
239 osc_addr[j] = 10'b0;
240 hst_reset[j] = 1'b0;
241 hst_addr[j] = 12'b0;
242 end
243
[45]244 case({mux_type,mux_chan})
245 3'b000, 3'b001, 3'b010, 3'b011:
[27]246 begin
[45]247 osc_reset[mux_chan] = mux_reset;
248 osc_addr[mux_chan] = mux_addr[9:0];
249 mux_max_byte = 2'd1;
250 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
[48]251 mux_num_addr = 16'd1023;
[27]252 end
[45]253
254 3'b100, 3'b101, 3'b110, 3'b111:
[27]255 begin
[45]256 hst_reset[mux_chan] = mux_reset;
257 hst_addr[mux_chan] = mux_addr[11:0];
258 mux_max_byte = 2'd2;
259 mux_min_addr = 16'd0;
[48]260 mux_num_addr = 16'd4095;
[27]261 end
262 endcase
263 end
[45]264
265 always @*
266 begin
267 case ({mux_type,mux_byte})
268 5'b000: mux_q = osc_q[mux_chan][7:0];
269 5'b001: mux_q = osc_q[mux_chan][15:8];
[35]270
[45]271 5'b100: mux_q = hst_q[mux_chan][7:0];
272 5'b101: mux_q = hst_q[mux_chan][15:8];
273 5'b110: mux_q = hst_q[mux_chan][23:16];
274
275 default: mux_q = 8'd0;
276 endcase
277 end
278
279
[30]280 always @(posedge CLK_50MHz)
281 begin
[37]282 if (~usb_fifo_rx_empty)
283 begin
284 led_reg <= 1'b0;
285 rx_counter <= 24'd0;
286 end
287 else
288 begin
289 if (&rx_counter)
290 begin
291 led_reg <= 1'b1;
292 end
293 else
294 begin
295 rx_counter <= rx_counter + 24'd1;
296 end
297 end
298
[35]299 case(state1)
[30]300 1:
301 begin
[37]302 usb_fifo_rx_rdreq <= 1'b1;
[30]303 usb_fifo_tx_wrreq <= 1'b0;
[45]304 mux_type <= 1'b0;
305 mux_chan <= 2'd0;
306 mux_byte <= 2'd0;
307 mux_reset <= 1'b0;
[35]308 state1 <= 4'd2;
[30]309 end
310
311 2:
312 begin
313 if (~usb_fifo_rx_empty)
314 begin
315 case (usb_fifo_rx_data)
[45]316 8'h40, 8'h41, 8'h42, 8'h43, 8'h50, 8'h51, 8'h52, 8'h53:
[30]317 begin
[37]318 usb_fifo_rx_rdreq <= 1'b0;
[45]319 mux_type <= usb_fifo_rx_data[4];
320 mux_chan <= usb_fifo_rx_data[1:0];
321 mux_reset <= 1'b1;
[35]322 state1 <= 4'd1;
[30]323 end
[45]324
325 8'h60, 8'h61, 8'h62, 8'h63, 8'h70, 8'h71, 8'h72, 8'h73:
[30]326 begin
[37]327 usb_fifo_rx_rdreq <= 1'b0;
[45]328 mux_type <= usb_fifo_rx_data[4];
329 mux_chan <= usb_fifo_rx_data[1:0];
[35]330 state1 <= 4'd3;
[30]331 end
[45]332
[44]333 8'h30:
[35]334 begin
[37]335 usb_fifo_rx_rdreq <= 1'b0;
[35]336 state1 <= 4'd1;
337 end
[45]338
[44]339 8'h31:
[35]340 begin
[37]341 usb_fifo_rx_rdreq <= 1'b0;
[35]342 tst_counter <= 11'd0;
343 state1 <= 4'd9;
344 end
[30]345 endcase
346 end
347 end
[45]348 // mux transfer
[30]349 3:
350 begin
[45]351 mux_addr <= mux_min_addr;
[48]352 mux_max_addr <= mux_min_addr + mux_num_addr;
[45]353 mux_byte <= 2'd0;
[35]354 state1 <= 4'd4;
355 end
356 4:
357 begin
[45]358 usb_fifo_tx_data <= mux_q;
359 usb_fifo_tx_wrreq <= 1'b1;
360 mux_byte <= 2'd1;
361 state1 <= 4'd5;
[30]362 end
[34]363 5:
364 begin
365 if (~usb_fifo_tx_full)
366 begin
[45]367 usb_fifo_tx_data <= mux_q;
368 if ((mux_byte == mux_max_byte) && (mux_addr == mux_max_addr))
[30]369 begin
[45]370 state1 <= 4'd6;
[30]371 end
[35]372 else
[34]373 begin
[45]374 if (mux_byte == mux_max_byte)
[35]375 begin
[45]376 mux_addr <= mux_addr + 16'd1;
377 mux_byte <= 2'd0;
[35]378 end
[45]379 else
380 begin
381 mux_byte <= mux_byte + 2'd1;
382 end
[34]383 end
[30]384 end
385 end
[45]386 6:
[30]387 begin
[35]388 if (~usb_fifo_tx_full)
[30]389 begin
[35]390 usb_fifo_tx_wrreq <= 1'b0;
391 state1 <= 4'd1;
[30]392 end
[34]393 end
[35]394 // tst transfer
[45]395 7:
[34]396 begin
[35]397 usb_fifo_tx_data <= tst_counter;
[34]398 usb_fifo_tx_wrreq <= 1'b1;
[35]399 tst_counter <= tst_counter + 11'd1;
[45]400 state1 <= 4'd8;
[34]401 end
[45]402 8:
[34]403 begin
404 if (~usb_fifo_tx_full)
[30]405 begin
[35]406 usb_fifo_tx_data <= tst_counter;
[48]407 if (tst_counter == 11'd0)
[34]408 begin
[45]409 state1 <= 4'd9;
[34]410 end
411 else
412 begin
[35]413 tst_counter <= tst_counter + 11'd1;
[34]414 end
[30]415 end
416 end
[45]417 9:
[30]418 begin
[34]419 if (~usb_fifo_tx_full)
[30]420 begin
[34]421 usb_fifo_tx_wrreq <= 1'b0;
[35]422 state1 <= 4'd1;
[30]423 end
424 end
[35]425
426 default:
427 begin
428 state1 <= 4'd1;
429 end
[30]430 endcase
431 end
[48]432
433 always @ (posedge tst_adc_clk)
[27]434 begin
435 case (state2)
436 1:
437 begin
[48]438 tst_adc_data <= 12'd0;
[35]439 state2 <= 4'd2;
[27]440 end
441
442 2:
443 begin
[48]444 tst_adc_data <= 12'd1024;
[35]445 state2 <= 4'd3;
[27]446 end
447
448 3:
449 begin
[48]450 tst_adc_data <= 12'd2048;
[35]451 state2 <= 4'd4;
[27]452 end
453
454 4:
455 begin
[48]456 tst_adc_data <= 12'd3072;
[35]457 state2 <= 4'd5;
[27]458 end
459
460 5:
461 begin
[48]462 tst_adc_data <= 12'd4095;
[35]463 state2 <= 4'd1;
[27]464 end
465
466 default:
467 begin
[35]468 state2 <= 4'd1;
[27]469 end
470 endcase
471 end
[48]472
[27]473endmodule
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