source: trunk/MultiChannelUSB/Paella.v@ 47

Last change on this file since 47 was 46, checked in by demin, 15 years ago

use loop for addr and reset initialisation
File size: 9.6 KB
RevLine 
[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
[41]15 input wire [2:0] ADC_D,
[27]16
17 output wire USB_SLRD,
18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 input wire USB_FLAGC,
[30]23 inout wire USB_PA0,
24 inout wire USB_PA1,
25 output wire USB_PA2,
26 inout wire USB_PA3,
27 output wire USB_PA4,
28 output wire USB_PA5,
29 output wire USB_PA6,
30 inout wire USB_PA7,
[27]31 inout wire [7:0] USB_PB,
32
33 output wire RAM_CLK,
34 output wire RAM_CE1,
35 output wire RAM_WE,
36 output wire [19:0] RAM_ADDR,
37 inout wire RAM_DQAP,
38 inout wire [7:0] RAM_DQA,
39 inout wire RAM_DQBP,
40 inout wire [7:0] RAM_DQB
41 );
42
43 // Turn output ports off
44 assign RAM_CLK = 1'b0;
45 assign RAM_CE1 = 1'b0;
46 assign RAM_WE = 1'b0;
47 assign RAM_ADDR = 20'h00000;
48
49 // Turn inout ports to tri-state
50 assign TRG = 4'bz;
51 assign CON_A = 7'bz;
52 assign CON_B = 16'bz;
53 assign CON_C = 13'bz;
[30]54 assign USB_PA0 = 1'bz;
55 assign USB_PA1 = 1'bz;
56 assign USB_PA3 = 1'bz;
57 assign USB_PA7 = 1'bz;
[27]58 assign RAM_DQAP = 1'bz;
59 assign RAM_DQA = 8'bz;
60 assign RAM_DQBP = 1'bz;
61 assign RAM_DQB = 8'bz;
62
[30]63
64 assign USB_PA2 = ~usb_rden;
65 assign USB_PA4 = usb_addr[0];
66 assign USB_PA5 = usb_addr[1];
67 assign USB_PA6 = ~usb_pktend;
68
[27]69 reg [31:0] counter;
[31]70 reg led_reg;
[30]71// assign LED = counter[24];
[31]72 assign LED = led_reg;
[27]73
74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[35]75 wire usb_fifo_aclr;
[30]76 reg usb_fifo_tx_wrreq;
77 reg usb_fifo_rx_rdreq;
[27]78 wire usb_fifo_tx_full, usb_fifo_rx_empty;
[30]79 reg [7:0] usb_fifo_tx_data;
80 wire [7:0] usb_fifo_rx_data;
[27]81 wire [1:0] usb_addr;
82
83 assign USB_SLRD = ~usb_rdreq;
84 assign USB_SLWR = ~usb_wrreq;
85
86 usb_fifo usb_fifo_unit
87 (
88 .usb_clk(USB_IFCLK),
89 .usb_data(USB_PB),
90 .usb_full(~USB_FLAGB),
91 .usb_empty(~USB_FLAGA),
92 .usb_wrreq(usb_wrreq),
93 .usb_rdreq(usb_rdreq),
94 .usb_rden(usb_rden),
95 .usb_pktend(usb_pktend),
96 .usb_addr(usb_addr),
[34]97
[27]98 .clk(CLK_50MHz),
99 .aclr(usb_fifo_aclr),
[34]100
101 .tx_full(usb_fifo_tx_full),
102 .tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
[27]103 .tx_data(usb_fifo_tx_data),
[34]104
[27]105 .rx_empty(usb_fifo_rx_empty),
[37]106 .rx_rdreq((~usb_fifo_rx_empty) & usb_fifo_rx_rdreq),
[35]107 .rx_q(usb_fifo_rx_data)
[27]108 );
109
[37]110 reg [23:0] rx_counter;
[35]111 reg [10:0] tst_counter;
112
[45]113 reg ana_reset [3:0];
114 wire ana_peak_ready [3:0];
115 wire [11:0] ana_peak [3:0];
[44]116
[35]117 reg [9:0] osc_counter;
[27]118
[45]119 reg osc_reset [3:0];
120 wire [9:0] osc_start_addr [3:0];
121 reg [9:0] osc_addr [3:0];
122 wire [15:0] osc_q [3:0];
[44]123 reg [15:0] osc_q_mux;
124
[45]125 reg hst_reset [3:0];
126 reg [11:0] hst_addr [3:0];
127 wire [23:0] hst_q [3:0];
[27]128
[45]129 reg mux_reset, mux_type;
130 reg [1:0] mux_chan, mux_byte, mux_max_byte;
131 reg [15:0] mux_addr, mux_min_addr, mux_max_addr;
132 reg [7:0] mux_q;
[44]133
[45]134 reg [3:0] state1, state2;
[27]135 reg adc_fifo_aclr;
136
[45]137 wire adc_clk [3:0];
[41]138
[45]139// reg [11:0] adc_data;
[41]140
[45]141 wire adc_data_ready [3:0];
142 wire [11:0] adc_data [3:0];
[41]143
[45]144 wire [11:0] raw_data [3:0];
145 wire [11:0] uwt_data [3:0];
146 wire [1:0] uwt_flag [3:0];
147
148 assign adc_clk[0] = ADC_FCO;
149 assign adc_clk[1] = ADC_FCO;
150 assign adc_clk[2] = ADC_FCO;
151 assign adc_clk[3] = CON_B[0];
152 assign adc_data[3] = CON_B[12:1];
153/*
[27]154 pll pll_unit(
155 .inclk0(CLK_50MHz),
156 .c0(adc_clk));
[45]157*/
[41]158/*
[38]159 altserial_flash_loader #(
160 .enable_shared_access("OFF"),
161 .enhanced_mode(1),
162 .intended_device_family("Cyclone III")) sfl_unit (
163 .noe(1'b0),
164 .asmi_access_granted(),
165 .asmi_access_request(),
166 .data0out(),
167 .dclkin(),
168 .scein(),
169 .sdoin());
[41]170*/
171 adc_lvds adc_lvds_unit (
172 .lvds_dco(ADC_DCO),
173 .lvds_fco(ADC_FCO),
174 .lvds_d(ADC_D),
[45]175 .adc_db(adc_data[0]),
176 .adc_dc(adc_data[1]),
177 .adc_dd(adc_data[2]));
[44]178
179 genvar i;
180 generate
[45]181 for (i = 0; i < 4; i = i + 1)
[44]182 begin : MCA_CHAIN
183 adc_fifo adc_fifo_unit (
[45]184 .adc_clk(adc_clk[i]),
185 .adc_data(adc_data[i]),
[44]186 .aclr(adc_fifo_aclr),
187 .rdclk(CLK_50MHz),
188 .ready(adc_data_ready[i]),
189 .raw_data(raw_data[i]),
190 .uwt_data({uwt_flag[i], uwt_data[i]}));
[27]191
[44]192 analyser analyser_unit (
193 .clk(CLK_50MHz),
194 .reset(ana_reset[i]),
195 .data_ready(adc_data_ready[i]),
196 .uwt_flag(uwt_flag[i]),
197 .uwt_data(uwt_data[i]),
198 .peak_ready(ana_peak_ready[i]),
199 .peak(ana_peak[i]));
200/*
201 histogram histogram_unit (
202 .clk(CLK_50MHz),
203 .reset(hst_reset[i]),
204 .data_ready(adc_data_ready[i]),
205 .data(raw_data[i]),
206 .address(hst_addr[i]),
207 .q(hst_q[i]));
208*/
209 histogram histogram_unit (
210 .clk(CLK_50MHz),
211 .reset(hst_reset[i]),
212 .data_ready(ana_peak_ready[i]),
213 .data(ana_peak[i]),
214 .address(hst_addr[i]),
215 .q(hst_q[i]));
216
217 oscilloscope oscilloscope_unit (
218 .clk(CLK_50MHz),
219 .reset(osc_reset[i]),
220 .data_ready(adc_data_ready[i]),
221 .raw_data(raw_data[i]),
222 .uwt_data(uwt_data[i]),
223 .threshold(16'd100),
224 .address(osc_addr[i]),
225 .start_address(osc_start_addr[i]),
226 .q(osc_q[i]));
227 end
228 endgenerate
[27]229
[30]230/*
[27]231 always @ (posedge adc_clk)
232 begin
233 counter <= counter + 32'd1;
234 end
[30]235*/
[27]236
[46]237 integer j;
238
[44]239 always @*
[27]240 begin
[46]241 for (j = 0; j < 4; j = j + 1)
242 begin
243 osc_reset[j] = 1'b0;
244 osc_addr[j] = 10'b0;
245 hst_reset[j] = 1'b0;
246 hst_addr[j] = 12'b0;
247 end
248
[45]249 case({mux_type,mux_chan})
250 3'b000, 3'b001, 3'b010, 3'b011:
[27]251 begin
[45]252 osc_reset[mux_chan] = mux_reset;
253 osc_addr[mux_chan] = mux_addr[9:0];
254 mux_max_byte = 2'd1;
255 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
256 mux_max_addr = {6'd0, osc_start_addr[mux_chan]} + 16'd1023;
[27]257 end
[45]258
259 3'b100, 3'b101, 3'b110, 3'b111:
[27]260 begin
[45]261 hst_reset[mux_chan] = mux_reset;
262 hst_addr[mux_chan] = mux_addr[11:0];
263 mux_max_byte = 2'd2;
264 mux_min_addr = 16'd0;
265 mux_max_addr = 16'd4095;
[27]266 end
267 endcase
268 end
[45]269
270 always @*
271 begin
272 case ({mux_type,mux_byte})
273 5'b000: mux_q = osc_q[mux_chan][7:0];
274 5'b001: mux_q = osc_q[mux_chan][15:8];
[35]275
[45]276 5'b100: mux_q = hst_q[mux_chan][7:0];
277 5'b101: mux_q = hst_q[mux_chan][15:8];
278 5'b110: mux_q = hst_q[mux_chan][23:16];
279
280 default: mux_q = 8'd0;
281 endcase
282 end
283
284
[30]285 always @(posedge CLK_50MHz)
286 begin
[37]287 if (~usb_fifo_rx_empty)
288 begin
289 led_reg <= 1'b0;
290 rx_counter <= 24'd0;
291 end
292 else
293 begin
294 if (&rx_counter)
295 begin
296 led_reg <= 1'b1;
297 end
298 else
299 begin
300 rx_counter <= rx_counter + 24'd1;
301 end
302 end
303
[35]304 case(state1)
[30]305 1:
306 begin
[37]307 usb_fifo_rx_rdreq <= 1'b1;
[30]308 usb_fifo_tx_wrreq <= 1'b0;
[45]309 mux_type <= 1'b0;
310 mux_chan <= 2'd0;
311 mux_byte <= 2'd0;
312 mux_reset <= 1'b0;
[35]313 state1 <= 4'd2;
[30]314 end
315
316 2:
317 begin
318 if (~usb_fifo_rx_empty)
319 begin
320 case (usb_fifo_rx_data)
[45]321 8'h40, 8'h41, 8'h42, 8'h43, 8'h50, 8'h51, 8'h52, 8'h53:
[30]322 begin
[37]323 usb_fifo_rx_rdreq <= 1'b0;
[45]324 mux_type <= usb_fifo_rx_data[4];
325 mux_chan <= usb_fifo_rx_data[1:0];
326 mux_reset <= 1'b1;
[35]327 state1 <= 4'd1;
[30]328 end
[45]329
330 8'h60, 8'h61, 8'h62, 8'h63, 8'h70, 8'h71, 8'h72, 8'h73:
[30]331 begin
[37]332 usb_fifo_rx_rdreq <= 1'b0;
[45]333 mux_type <= usb_fifo_rx_data[4];
334 mux_chan <= usb_fifo_rx_data[1:0];
[35]335 state1 <= 4'd3;
[30]336 end
[45]337
[44]338 8'h30:
[35]339 begin
[37]340 usb_fifo_rx_rdreq <= 1'b0;
[35]341 state1 <= 4'd1;
342 end
[45]343
[44]344 8'h31:
[35]345 begin
[37]346 usb_fifo_rx_rdreq <= 1'b0;
[35]347 tst_counter <= 11'd0;
348 state1 <= 4'd9;
349 end
[30]350 endcase
351 end
352 end
[45]353 // mux transfer
[30]354 3:
355 begin
[45]356 mux_addr <= mux_min_addr;
357 mux_byte <= 2'd0;
[35]358 state1 <= 4'd4;
359 end
360 4:
361 begin
[45]362 usb_fifo_tx_data <= mux_q;
363 usb_fifo_tx_wrreq <= 1'b1;
364 mux_byte <= 2'd1;
365 state1 <= 4'd5;
[30]366 end
[34]367 5:
368 begin
369 if (~usb_fifo_tx_full)
370 begin
[45]371 usb_fifo_tx_data <= mux_q;
372 if ((mux_byte == mux_max_byte) && (mux_addr == mux_max_addr))
[30]373 begin
[45]374 state1 <= 4'd6;
[30]375 end
[35]376 else
[34]377 begin
[45]378 if (mux_byte == mux_max_byte)
[35]379 begin
[45]380 mux_addr <= mux_addr + 16'd1;
381 mux_byte <= 2'd0;
[35]382 end
[45]383 else
384 begin
385 mux_byte <= mux_byte + 2'd1;
386 end
[34]387 end
[30]388 end
389 end
[45]390 6:
[30]391 begin
[35]392 if (~usb_fifo_tx_full)
[30]393 begin
[35]394 usb_fifo_tx_wrreq <= 1'b0;
395 state1 <= 4'd1;
[30]396 end
[34]397 end
[35]398 // tst transfer
[45]399 7:
[34]400 begin
[35]401 usb_fifo_tx_data <= tst_counter;
[34]402 usb_fifo_tx_wrreq <= 1'b1;
[35]403 tst_counter <= tst_counter + 11'd1;
[45]404 state1 <= 4'd8;
[34]405 end
[45]406 8:
[34]407 begin
408 if (~usb_fifo_tx_full)
[30]409 begin
[35]410 usb_fifo_tx_data <= tst_counter;
411 if (tst_counter == 11'd0) //(&osc_counter)
[34]412 begin
[45]413 state1 <= 4'd9;
[34]414 end
415 else
416 begin
[35]417 tst_counter <= tst_counter + 11'd1;
[34]418 end
[30]419 end
420 end
[45]421 9:
[30]422 begin
[34]423 if (~usb_fifo_tx_full)
[30]424 begin
[34]425 usb_fifo_tx_wrreq <= 1'b0;
[35]426 state1 <= 4'd1;
[30]427 end
428 end
[35]429
430 default:
431 begin
432 state1 <= 4'd1;
433 end
[30]434 endcase
435 end
[45]436/*
[27]437 always @ (posedge adc_clk)
438 begin
439 case (state2)
440 1:
441 begin
442 adc_data <= 12'd0;
[35]443 state2 <= 4'd2;
[27]444 end
445
446 2:
447 begin
448 adc_data <= 12'd1024;
[35]449 state2 <= 4'd3;
[27]450 end
451
452 3:
453 begin
454 adc_data <= 12'd2048;
[35]455 state2 <= 4'd4;
[27]456 end
457
458 4:
459 begin
460 adc_data <= 12'd3072;
[35]461 state2 <= 4'd5;
[27]462 end
463
464 5:
465 begin
466 adc_data <= 12'd4095;
[35]467 state2 <= 4'd1;
[27]468 end
469
470 default:
471 begin
[35]472 state2 <= 4'd1;
[27]473 end
474 endcase
475 end
[45]476*/
[27]477endmodule
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