Timeline
Sep 23, 2009:
- 9:46 PM Changeset [63] by
- add parameters for number of channels and channel resolution
- 9:45 PM Changeset [62] by
- add polarity flag
- 9:44 PM Changeset [61] by
- add interface for parallel ADC with unreliable clock
- 9:42 PM Changeset [60] by
- interface for parallel ADC with unreliable clock
Sep 18, 2009:
- 1:40 PM Changeset [59] by
- move control and test code to separate modules
- 1:39 PM Changeset [58] by
- code cleanup
Sep 17, 2009:
- 6:39 PM Changeset [57] by
- switch to direct instantiation of altsyncram and dcfifo
- 6:37 PM Changeset [56] by
- switch to direct instantiation of altsyncram
- 6:37 PM Changeset [55] by
- add pll for lvds interface
- 6:35 PM Changeset [54] by
- adapat memory access to normal memory clock
- 6:32 PM Changeset [53] by
- add signal invertor
- 6:31 PM Changeset [52] by
- switch to normal memory clock
Sep 16, 2009:
- 12:52 PM Changeset [51] by
- first attempt to use normal memory clock
- 12:51 PM Changeset [50] by
- fix peak detection logic and add peak threshold
- 12:37 PM Changeset [49] by
- add registers for output data
- 12:35 PM Changeset [48] by
- cleanup test circuit
- 12:34 PM Changeset [47] by
- switch to direct instantiation of altsyncram
- 12:32 PM Changeset [46] by
- use loop for addr and reset initialisation
Sep 15, 2009:
- 3:27 AM Changeset [45] by
- add fourth channel and switch from 32 to 24 bit histogram
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