Changeset 184 for trunk/3DEES/classifier.v
- Timestamp:
- Jan 27, 2014, 3:49:22 PM (11 years ago)
- File:
-
- 1 edited
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trunk/3DEES/classifier.v (modified) (7 diffs)
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trunk/3DEES/classifier.v
r183 r184 5 5 ( 6 6 input wire clock, frame, reset, 7 input wire [1 4*width-1:0] cfg_data,7 input wire [18*width-1:0] cfg_data, 8 8 input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F} 9 9 input wire [5:0] inp_flag, 10 output wire [ 5:0] out_data,10 output wire [6:0] out_data, 11 11 output wire out_flag 12 12 ); 13 13 14 14 reg out_flag_reg [2:0], out_flag_next [2:0]; 15 reg [ 5:0] out_data_reg [2:0], out_data_next [2:0];15 reg [6:0] out_data_reg [2:0], out_data_next [2:0]; 16 16 reg [5:0] inp_flag_reg, inp_flag_next; 17 17 reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0]; … … 22 22 wire [width-1:0] inp_data_wire [5:0]; 23 23 wire [3:0] int_pipe_wire [5:0]; 24 wire [1 3:0] int_comp_wire;24 wire [15:0] int_comp_wire; 25 25 26 26 integer i; … … 35 35 36 36 generate 37 assign int_comp_wire[0] = (inp_data_reg[0] > cfg_data[width-1:0]); 38 assign int_comp_wire[1] = (inp_data_reg[1] > cfg_data[2*width-1:width]); 37 assign int_comp_wire[0] = inp_flag_reg[0] & (inp_data_reg[0] < cfg_data[width-1:0]); 38 assign int_comp_wire[1] = inp_flag_reg[0] & (inp_data_reg[0] > cfg_data[2*width-1:1*width]) & (inp_data_reg[0] < cfg_data[3*width-1:2*width]); 39 40 assign int_comp_wire[2] = inp_flag_reg[1] & (inp_data_reg[1] < cfg_data[4*width-1:3*width]); 41 assign int_comp_wire[3] = inp_flag_reg[1] & (inp_data_reg[1] > cfg_data[5*width-1:4*width]) & (inp_data_reg[1] < cfg_data[6*width-1:5*width]); 42 39 43 for (j = 0; j < 4; j = j + 1) 40 44 begin : CLASSIFIER_COMPARTORS 41 assign int_comp_wire[j*3+0+ 2] = (inp_data_reg[j+2] > cfg_data[(j*3+0+2)*width+width-1:(j*3+0+2)*width]);42 assign int_comp_wire[j*3+1+ 2] = (inp_data_reg[j+2] > cfg_data[(j*3+1+2)*width+width-1:(j*3+1+2)*width]);43 assign int_comp_wire[j*3+2+ 2] = (inp_data_reg[j+2] > cfg_data[(j*3+2+2)*width+width-1:(j*3+2+2)*width]);45 assign int_comp_wire[j*3+0+4] = (inp_data_reg[j+2] > cfg_data[(j*3+0+6)*width+width-1:(j*3+0+6)*width]); 46 assign int_comp_wire[j*3+1+4] = (inp_data_reg[j+2] > cfg_data[(j*3+1+6)*width+width-1:(j*3+1+6)*width]); 47 assign int_comp_wire[j*3+2+4] = (inp_data_reg[j+2] > cfg_data[(j*3+2+6)*width+width-1:(j*3+2+6)*width]); 44 48 end 45 49 endgenerate … … 168 172 out_flag_next[2] = out_flag_reg[1] & (out_data_reg[1] > out_data_reg[0]); 169 173 170 int_pipe_next[0] = {int_pipe_reg[0][14:0], int_comp_wire[0]}; 171 int_pipe_next[1] = {int_pipe_reg[1][14:0], int_comp_wire[1]}; 172 for (i = 2; i < 8; i = i + 1) 174 for (i = 0; i < 4; i = i + 1) 175 begin 176 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i]}; 177 end 178 for (i = 4; i < 8; i = i + 1) 173 179 begin 174 180 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-2]}; … … 176 182 for (i = 8; i < 20; i = i + 1) 177 183 begin 178 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i- 6]};184 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-4]}; 179 185 end 180 186 … … 182 188 begin 183 189 case (int_pipe_wire[i+2][2:0]) 184 3'b000: int_data_next[i] = 2' d0;185 3'b001: int_data_next[i] = 2' d1;186 3'b011: int_data_next[i] = 2' d2;187 3'b111: int_data_next[i] = 2' d3;190 3'b000: int_data_next[i] = 2'b00; 191 3'b001: int_data_next[i] = 2'b01; 192 3'b011: int_data_next[i] = 2'b10; 193 3'b111: int_data_next[i] = 2'b11; 188 194 default: int_data_next[i] = 2'd0; 189 195 endcase 190 196 end 191 197 192 int_temp_next[0] = {int_pipe_wire[1], int_pipe_wire[0][3]^int_pipe_wire[0][2]};198 int_temp_next[0] = {int_pipe_wire[1], ^int_pipe_wire[0]}; 193 199 int_temp_next[1] = {1'b0, int_pipe_wire[0]}; 194 200 195 201 case (int_temp_reg[0][4:0]) 196 5'b00011: out_data_next[0][3:0] = {2' d0, int_data_next[0]};197 5'b00111: out_data_next[0][3:0] = {2' d1, int_data_next[1]};198 5'b01111: out_data_next[0][3:0] = {2' d2, int_data_next[2]};199 5'b11111: out_data_next[0][3:0] = {2' d3, int_data_next[3]};202 5'b00011: out_data_next[0][3:0] = {2'b00, int_data_next[0]}; 203 5'b00111: out_data_next[0][3:0] = {2'b01, int_data_next[1]}; 204 5'b01111: out_data_next[0][3:0] = {2'b10, int_data_next[2]}; 205 5'b11111: out_data_next[0][3:0] = {2'b11, int_data_next[3]}; 200 206 default: out_flag_next[0] = 1'b0; 201 207 endcase … … 203 209 case (int_temp_reg[1][3:0]) 204 210 // S1_F, electron 205 4'b0 100: out_data_next[0][5:4] = 2'd0;211 4'b0001: out_data_next[0][6:4] = 3'b100; 206 212 207 213 // S1_F, proton 208 4'b0 101: out_data_next[0][5:4] = 2'd1;214 4'b0010: out_data_next[0][6:4] = 3'b101; 209 215 210 216 // S1_S, electron 211 4'b 1000: out_data_next[0][5:4] = 2'd2;217 4'b0100: out_data_next[0][6:4] = 3'b110; 212 218 213 219 // S1_S, proton 214 4'b10 10: out_data_next[0][5:4] = 2'd3;220 4'b1000: out_data_next[0][6:4] = 3'b111; 215 221 216 222 default: out_flag_next[0] = 1'b0;
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