source: trunk/3DEES/classifier.v@ 183

Last change on this file since 183 was 183, checked in by demin, 11 years ago

fix classifier and add bin number to osc mux
File size: 6.2 KB
Line 
1module classifier
2 #(
3 parameter width = 12 // bit width of the input data (unsigned)
4 )
5 (
6 input wire clock, frame, reset,
7 input wire [14*width-1:0] cfg_data,
8 input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F}
9 input wire [5:0] inp_flag,
10 output wire [5:0] out_data,
11 output wire out_flag
12 );
13
14 reg out_flag_reg [2:0], out_flag_next [2:0];
15 reg [5:0] out_data_reg [2:0], out_data_next [2:0];
16 reg [5:0] inp_flag_reg, inp_flag_next;
17 reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0];
18 reg [15:0] int_pipe_reg [19:0], int_pipe_next [19:0];
19 reg [1:0] int_data_reg [3:0], int_data_next [3:0];
20 reg [4:0] int_temp_reg [1:0], int_temp_next [1:0];
21
22 wire [width-1:0] inp_data_wire [5:0];
23 wire [3:0] int_pipe_wire [5:0];
24 wire [13:0] int_comp_wire;
25
26 integer i;
27 genvar j;
28
29 generate
30 for (j = 0; j < 6; j = j + 1)
31 begin : CLASSIFIER_INPUT_DATA
32 assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
33 end
34 endgenerate
35
36 generate
37 assign int_comp_wire[0] = (inp_data_reg[0] > cfg_data[width-1:0]);
38 assign int_comp_wire[1] = (inp_data_reg[1] > cfg_data[2*width-1:width]);
39 for (j = 0; j < 4; j = j + 1)
40 begin : CLASSIFIER_COMPARTORS
41 assign int_comp_wire[j*3+0+2] = (inp_data_reg[j+2] > cfg_data[(j*3+0+2)*width+width-1:(j*3+0+2)*width]);
42 assign int_comp_wire[j*3+1+2] = (inp_data_reg[j+2] > cfg_data[(j*3+1+2)*width+width-1:(j*3+1+2)*width]);
43 assign int_comp_wire[j*3+2+2] = (inp_data_reg[j+2] > cfg_data[(j*3+2+2)*width+width-1:(j*3+2+2)*width]);
44 end
45 endgenerate
46
47 generate
48 for (j = 0; j < 4; j = j + 1)
49 begin : CLASSIFIER_PIPELINE
50 assign int_pipe_wire[0][j] = (|int_pipe_reg[j]);
51 assign int_pipe_wire[1][j] = (|int_pipe_reg[j+4]);
52 assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j*3+0+8]);
53 assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j*3+1+8]);
54 assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j*3+2+8]);
55 assign int_pipe_wire[j+2][3] = 1'b0;
56 end
57 endgenerate
58
59 always @(posedge clock)
60 begin
61 if (reset)
62 begin
63 inp_flag_reg <= {(6){1'b0}};
64 for (i = 0; i < 3; i = i + 1)
65 begin
66 out_data_reg[i] <= {(6){1'b0}};
67 out_flag_reg[i] <= 1'b0;
68 end
69 for (i = 0; i < 6; i = i + 1)
70 begin
71 inp_data_reg[i] <= {(width){1'b0}};
72 end
73 for (i = 0; i < 20; i = i + 1)
74 begin
75 int_pipe_reg[i] <= {(16){1'b0}};
76 end
77 for (i = 0; i < 4; i = i + 1)
78 begin
79 int_data_reg[i] <= {(2){1'b0}};
80 end
81 for (i = 0; i < 2; i = i + 1)
82 begin
83 int_temp_reg[i] <= {(5){1'b0}};
84 end
85 end
86 else
87 begin
88 inp_flag_reg <= inp_flag_next;
89 for (i = 0; i < 3; i = i + 1)
90 begin
91 out_data_reg[i] <= out_data_next[i];
92 out_flag_reg[i] <= out_flag_next[i];
93 end
94 for (i = 0; i < 6; i = i + 1)
95 begin
96 inp_data_reg[i] <= inp_data_next[i];
97 end
98 for (i = 0; i < 20; i = i + 1)
99 begin
100 int_pipe_reg[i] <= int_pipe_next[i];
101 end
102 for (i = 0; i < 4; i = i + 1)
103 begin
104 int_data_reg[i] <= int_data_next[i];
105 end
106 for (i = 0; i < 2; i = i + 1)
107 begin
108 int_temp_reg[i] <= int_temp_next[i];
109 end
110 end
111 end
112
113 always @*
114 begin
115 inp_flag_next = inp_flag_reg;
116 for (i = 0; i < 3; i = i + 1)
117 begin
118 out_data_next[i] = out_data_reg[i];
119 out_flag_next[i] = out_flag_reg[i];
120 end
121 for (i = 0; i < 6; i = i + 1)
122 begin
123 inp_data_next[i] = inp_data_reg[i];
124 end
125 for (i = 0; i < 20; i = i + 1)
126 begin
127 int_pipe_next[i] = int_pipe_reg[i];
128 end
129 for (i = 0; i < 4; i = i + 1)
130 begin
131 int_data_next[i] = int_data_reg[i];
132 end
133 for (i = 0; i < 2; i = i + 1)
134 begin
135 int_temp_next[i] = int_temp_reg[i];
136 end
137
138 if (frame)
139 begin
140 inp_flag_next = inp_flag;
141 for (i = 0; i < 6; i = i + 1)
142 begin
143 inp_data_next[i] = inp_data_wire[i];
144 end
145
146 if (out_flag_reg[2])
147 begin
148 for (i = 0; i < 3; i = i + 1)
149 begin
150 out_data_next[i] = {(6){1'b0}};
151 out_flag_next[i] = 1'b0;
152 end
153 for (i = 0; i < 20; i = i + 1)
154 begin
155 int_pipe_next[i] = {(16){1'b0}};
156 end
157 int_temp_next[0] = {(5){1'b0}};
158 int_temp_next[1] = {(5){1'b0}};
159 end
160 else
161 begin
162 out_data_next[0] = {(6){1'b0}};
163 out_data_next[1] = out_data_reg[0];
164 out_data_next[2] = out_data_reg[1];
165
166 out_flag_next[0] = 1'b1;
167 out_flag_next[1] = out_flag_reg[0];
168 out_flag_next[2] = out_flag_reg[1] & (out_data_reg[1] > out_data_reg[0]);
169
170 int_pipe_next[0] = {int_pipe_reg[0][14:0], int_comp_wire[0]};
171 int_pipe_next[1] = {int_pipe_reg[1][14:0], int_comp_wire[1]};
172 for (i = 2; i < 8; i = i + 1)
173 begin
174 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-2]};
175 end
176 for (i = 8; i < 20; i = i + 1)
177 begin
178 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-6]};
179 end
180
181 for (i = 0; i < 4; i = i + 1)
182 begin
183 case (int_pipe_wire[i+2][2:0])
184 3'b000: int_data_next[i] = 2'd0;
185 3'b001: int_data_next[i] = 2'd1;
186 3'b011: int_data_next[i] = 2'd2;
187 3'b111: int_data_next[i] = 2'd3;
188 default: int_data_next[i] = 2'd0;
189 endcase
190 end
191
192 int_temp_next[0] = {int_pipe_wire[1], int_pipe_wire[0][3]^int_pipe_wire[0][2]};
193 int_temp_next[1] = {1'b0, int_pipe_wire[0]};
194
195 case (int_temp_reg[0][4:0])
196 5'b00011: out_data_next[0][3:0] = {2'd0, int_data_next[0]};
197 5'b00111: out_data_next[0][3:0] = {2'd1, int_data_next[1]};
198 5'b01111: out_data_next[0][3:0] = {2'd2, int_data_next[2]};
199 5'b11111: out_data_next[0][3:0] = {2'd3, int_data_next[3]};
200 default: out_flag_next[0] = 1'b0;
201 endcase
202
203 case (int_temp_reg[1][3:0])
204 // S1_F, electron
205 4'b0100: out_data_next[0][5:4] = 2'd0;
206
207 // S1_F, proton
208 4'b0101: out_data_next[0][5:4] = 2'd1;
209
210 // S1_S, electron
211 4'b1000: out_data_next[0][5:4] = 2'd2;
212
213 // S1_S, proton
214 4'b1010: out_data_next[0][5:4] = 2'd3;
215
216 default: out_flag_next[0] = 1'b0;
217 endcase
218 end
219 end
220 end
221
222// assign out_data = {1'd0, int_pipe_wire[1+2][2:0], int_data_reg[1]};
223// assign out_data = {1'd0, int_comp_wire[0], int_temp_reg[1][3:0]};
224// assign out_data = {1'd0, int_temp_reg[0][4:0]};
225 assign out_data = out_data_reg[2];
226 assign out_flag = out_flag_reg[2];
227
228endmodule
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